FM24CL64B(2014) Ver la hoja de datos (PDF) - Cypress Semiconductor
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FM24CL64B Datasheet PDF : 19 Pages
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FM24CL64B
Pinouts
Figure 1. 8-pin SOIC pinout
A0 1
8
A1 2 Top View 7
not to scale
A2 3
6
VSS 4
5
VDD
WP
SCL
SDA
Figure 2. 8-pin TDFN pinout
O
A0 1
8 VDD
A1 2
A2 3
EXPOSED
PAD
7 WP
6 SCL
VSS 4
5 SDA
Top View
not to scale
Pin Definitions
Pin Name I/O Type
Description
A2-A0
SDA
SCL
Input
Device Select Address 2-0. These pins are used to select one of up to 8 devices of the same type on
the same I2C bus. To select the device, the address value on the three pins must match the corre-
sponding bits contained in the slave address. The address pins are pulled down internally.
Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended
to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
Input
Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
WP
Input Write Protect. When tied to VDD, addresses in the entire memory map will be write-protected. When
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
VSS
VDD
EXPOSED
PAD
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect The EXPOSED PAD on the bottom of 8-pin TDFN package is not connected to the die. The EXPOSED
PAD should be left floating.
Document Number: 001-84458 Rev. *D
Page 3 of 19
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