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MPC8541EPXAJF

PowerQUICC™ III Integrated Communications Processor Hardware Specification

Freescale Semiconductor 

System Design Information

From Target

Board Sources

(if any)

SRESET

HRESET

10 kΩ

OVDD

SRESET 6

10 kΩ

HRESET1

COP_HRESET

13

COP_SRESET

11

5

10 kΩ

10 kΩ

10 kΩ

12

34

56

78

9 10

11 12

13

KEY

No pin

15 16

COP Connector

Physical Pinout

COP_TRST

4

6 COP_VDD_SENSE2

5 NC

COP_CHKSTP_OUT

15

14 3

COP_CHKSTP_IN

8

COP_TMS

9

COP_TDO

1

COP_TDI

3

COP_TCK

7

2 NC

10 NC

10 Ω

10 kΩ

10 kΩ

10 kΩ

10 kΩ

TRST1

CKSTP_OUT

CKSTP_IN

TMS

TDO

TDI

TCK

12

4

16

Notes:

1. The COP port and target board should be able to independently assert HRESET and TRST to the processor

in order to fully control the processor as shown here.

2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid

accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

6. Asserting SRESET causes a machine check interrupt to the e500 core.

Figure 52. JTAG Interface Connection

MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2

82

Freescale Semiconductor

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