WT61P8 Ver la hoja de datos (PDF) - Weltrend Semiconductor
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WT61P8 Datasheet PDF : 54 Pages
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WT61P8 v1.01
Flat Panel Display Control Sub-MCU
4.1.4. 8052 Timer0,Timer1,Timer2,Timer3,UART0,UART1,INT1,INT2,INT3
INT1/INT2 is cause by 1st DDC,2nd DDC,HV DPMS detector, IR detector, CEC detector, Key pad ADC,
input toggle interruption.
INT3 is cause by slave IIC
If UART0 is used, the EN_UART0_IO register has to be set “1”.
If UART1 is used, the EN_UART1_IO register has to be set “1”.
4.1.5. SFR(SPECIAL FUNCTION REGISTER) MAP
F8
F0
B
E8 T3CON
RCAP3L RCAP3H TL3
TH3
E0 ACC
D8 SCON1 SBUF1 SBRG1
D0 PSW
C8 T2CON
RCAP2L RCAP2H TL2
TH2
C0 XICON
B8
IP
IP2
B0
P3
A8
IE
IE2
A0
P2
98 SCON SBUF SBRG0
90
P1
88 TCON TMOD
TL0
TL1
TH0
TH1
80
P0
SP
DPL
DPH
CKSEL
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
PCON 87
bit addressable
Nine-source interrupt information:
Interrupt Source
Vector
Address
Timer/Counter 0
0BH
External Interrupt 1
13H
Timer/Counter 1
1BH
Serial Port 0 (UART0)
23H
Timer/Counter 2
2BH
Serial Port 1 (UART1)
33H
External Interrupt 2
3BH
External Interrupt 3
43H
Timer/Counter 3
4BH
Polling Sequence Enabled required Interrupt type
within Priority level
settings
edge/level
1
IE.1
--
2
IE.2
TCON.2
3
IE.3
--
4
IE.4
--
5
IE.5
--
6
IE.6
--
7
XICON.2
XICON.0
8
XICON.6
XICON.4
9(lowest)
IE2.0
--
XICON (8052 interrupt enable and priority register) Address : C0H
Index Default R/W Bit
Name
Description
C0 00 R/W 7 PX3
External interrupt 3 priority high if set
Copyright© 2008 Weltrend Semiconductor, Inc. All Rights Reserved.
Weltrend reserves right to modify all information contained in this document without notice.
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