WT61P8 Ver la hoja de datos (PDF) - Weltrend Semiconductor
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WT61P8 Datasheet PDF : 54 Pages
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WT61P8 v1.01
Flat Panel Display Control Sub-MCU
6 EX3
External interrupt 3 enable if set
5 IE3
If IT3 = 1, IE3 is set/cleared automatically by hardware
when interrupt is detected/serviced
4 IT3
External interrupt 3 is falling-edge/low-level triggered when
this bit is set/cleared by software
3 PX2
External interrupt 2 priority high if set
2 EX2
External interrupt 2 enable if set
1 IE2
If IT2 = 1, IE2 is set/cleared automatically by hardware
when interrupt is detected/serviced
0 IT2
External interrupt 2 is falling-edge/low-level triggered when
this bit is set/cleared by software
The XICON register is bit-addressable but is not a standard register in the standard 8052. Its address is
at C0H. To set/clear bits in the XICON register, one can use the “SETB (/CLR) bit” instruction. For example,
“SETB C2H” sets the EX2 bit of XICON.
IE (8052 interrupt enable register) Address : A8H
7
6
5
4
3
2
1
0
EA
ES1
ET2
ES
ET1
EX1
ET0
EX0
ES1 :IE.6, Enables/disables the Serial Port 1 interrupt. If ES1 = 0, the Serial Port 1 interrupt is disabled.
IE2 (8052 interrupt enable register2) Address : A9h
7
6
5
4
3
2
1
0
ET3
ET3:IE2.0, Enables or disables the Timer 3 interrupt. If ET3=0, the Timer 3 interrupt is disabled.
IP (8052 interrupt priority register) Address : B8H
7
6
5
4
3
2
1
0
PS1
PT2
PS
PT1
PX1
PT0
PX0
“PS1” : IP.6, Define the serial port 1 interrupt priority level. PS1 = 1 program it to higher priority level.
IP2 (8052 interrupt priority register2) Address : B9h
7
6
5
4
3
2
1
0
PT3
“PT3”: IP2.0, Define the Timer 3 interrupt priority level. PT3 = 1 program it to higher priority level.
SCON1 (8052 UART1 control register) Address : D8H
7
6
5
4
3
SM0_1
SM0_2
SM0_3
REN_1
TB8_1
The additional serial port is similar as 8052’s UART.
2
RB8_1
1
TI_1
0
RI_1
SBUF1 (8052 UART1 buffer) Address : D9H
7
6
5
4
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4
3
SBUF1.3
2
SBUF1.2
1
SBUF1.1
0
SBUF1.0
PCON (8052 power control register) Address : 87H
7
6
5
4
3
2
1
0
SMOD1 SMOD2
GF1
GF0
PD
IDL
SBRG0 (8052 UART0 baud rate control register) Address : 9AH
7
6
5
4
3
2
SBRG0EN SBRG0.6 SBRG0.5 SBRG0.4 SBRG0.3 SBRG0.2
1
SBRG0.1
0
SBRG0.0
SBRG1 (8052 UART1 baud rate control register) Address : DAH
7
6
5
4
3
2
SBRG1EN SBRG1.6 SBRG1.5 SBRG1.4 SBRG1.3 SBRG1.2
1
SBRG1.1
0
SBRG1.0
Copyright© 2008 Weltrend Semiconductor, Inc. All Rights Reserved.
Weltrend reserves right to modify all information contained in this document without notice.
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