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BD6376GUL_12 Datasheet PDF : 14 Pages
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BD6376GUL
Datasheet
●Operational Notes
1) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range
(Topr) may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open
mode) when such damage is suffered. The implementation of a physical safety measure such as a fuse should be
considered when use of the IC in a special mode where the absolute maximum ratings may be exceeded is
anticipated.
2) Power supply pins and lines
None of the VM line for the H-bridge is internally connected to the VCC power supply line, which is only for the
control logic or analog circuit. Therefore, the VM and VCC lines can be driven at different voltages. Although these
lines can be connected to a common power supply, do not open the power supply pin but connect it to the power
supply externally.
Regenerated current may flow as a result of the motor's back electromotive force. Insert capacitors between the
power supply and ground pins to serve as a route for regenerated current. Determine the capacitance in full
consideration of all the characteristics of the electrolytic capacitor, because the electrolytic capacitor may loose
some capacitance at low temperatures. If the connected power supply does not have sufficient current absorption
capacity, regenerative current will cause the voltage on the power supply line to rise, which combined with the
product and its peripheral circuitry may exceed the absolute maximum ratings. It is recommended to implement a
physical safety measure such as the insertion of a voltage clamp diode between the power supply and ground pins.
For this IC with 2 power supplies and a part consists of the CMOS block, it is possible that rush current may flow
instantaneously due to the internal powering sequence and delays, and to the unstable internal logic, respectively.
Therefore, give special consideration to power coupling capacitance, width of power and ground wirings, and
routing of wiring.
3) Ground pins and lines
Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the
GND at any time, regardless of whether it is a transient signal or not.
When using both small signal GND and large current PGND patterns, it is recommended to isolate the two ground
patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and
voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful
not to change the GND wiring pattern of any external components, either.
The power supply and ground lines must be as short and thick as possible to reduce line impedance.
4) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating
conditions.
5) Actions in strong magnetic field
Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to
malfunction.
6) ASO
When using the IC, set the output transistor for the motor so that it does not exceed absolute maximum ratings or
ASO.
7) Thermal shutdown circuit
This IC incorporates a TSD (thermal shutdown) circuit. If the temperature of the chip reaches the following
temperature, the motor coil output will be opened. The TSD circuit is designed only to shut the IC off to prevent
runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use
the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed.
TSD ON temperature [°C] (Typ.)
Hysteresis temperature [°C] (Typ.)
175
20
8) Application example
The application circuit is recommended for use. Make sure to confirm the adequacy of the
characteristics. When using the circuit with changes to the external circuit constants, make sure to
leave an adequate margin for external components including static and transitional characteristics as
well as dispersion of the IC.
Pin A
Resistor
Pin A
Pin B
B
C
E
Transistor (NPN)
Pin B
N
P+
N
Parasitic element
P
P+
N
P substrate
GND
Parasitic
element
N P+
N
P
P+
N
P substrate
Parasitic element
GND
GND
Figure 12. Example of Simple IC Architecture
B
C
E
Other adjacent
elements
Parasitic
GND element
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
9/11
TSZ02201-0H3H0B600310-1-2
3.AUG.2012 Rev.001
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