M27C256B-25C1 Ver la hoja de datos (PDF) - STMicroelectronics

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M27C256B-25C1

256 Kbit (32Kb × 8) UV EPROM and OTP EPROM

STMicroelectronics 

M27C256B

Device operation

2.4

System considerations

The power switching characteristics of Advance CMOS EPROMs require careful decoupling

of the devices. The supply current, ICC, has three segments that are of interest to the system

designer: the standby current level, the active current level, and transient current peaks that

are produced by the falling and rising edges of E. The magnitude of this transient current

peaks is dependent on the capacitive and inductive loading of the device at the output. The

associated transient voltage peaks can be suppressed by complying with the two line output

control and by properly selected decoupling capacitors. It is recommended that a 0.1µF

ceramic capacitor be used on every device between VCC and VSS. This should be a high

frequency capacitor of low inherent inductance and should be placed as close to the device

as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and

VSS for every eight devices. The bulk capacitor should be located near the power supply

connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused

) by the inductive effects of PCB traces.

duct(s 2.5

Programming

ro When delivered (and after each erasure for UV EPROM), all bits of the M27C256B are in the

P "1" state. Data is introduced by selectively programming "0"s into the desired bit locations.

te Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word.

le The only way to change a '0' to a '1' is by die exposure to ultraviolet light (UV EPROM). The

o M27C256B is in the programming mode when VPP input is at 12.75V, G is at VIH and E is

s pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output

b pins. The levels required for the address and data inputs are TTL. VCC is specified to be

O 6.25V ± 0.25 V.

t(s) - 2.6

PRESTO II programming algorithm

uc PRESTO II Programming Algorithm allows to program the whole array with a guaranteed

d margin, in a typical time of 3.5 seconds. Programming with PRESTO II involves the

ro application of a sequence of 100µs program pulses to each byte until a correct verify occurs

P (see Figure 4.). During programming and verify operation, a MARGIN MODE circuit is

teautomatically activated in order to guarantee that each cell is programmed with enough

margin. No overprogram pulse is applied since the verify in MARGIN MODE provides

Obsolenecessary margin to each programmed cell.

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