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LTC2140-12 Ver la hoja de datos (PDF) - Linear Technology

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Fabricante
LTC2140-12 Datasheet PDF : 36 Pages
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LTC2142-12/
LTC2141-12/LTC2140-12
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2142-12
LTC2141-12
LTC2140-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
OVDD
IVDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9
V
l
50.9 TBD
51.3
35.9 TBD
36.2
26.9 TBD
mA
27
mA
IOVDD
PDISS
Digital Supply Current
Power Dissipation
LVDS Output Mode
Sine Wave Input, OVDD = 1.2V
DC Input
l
Sine Wave Input, OVDD = 1.2V
3.8
91.6 TBD
96.9
2.4
64.6 TBD
68
1.5
mA
48.4 TBD mW
50.4
mW
VDD
Analog Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
OVDD Output Supply Voltage (Note 10)
l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9
V
IVDD
Analog Supply Current Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
52.6
53.8 TBD
37.4
38.7 TBD
28.3
mA
29.5 TBD
mA
IOVDD Digital Supply Current Sine Input, 1.75mA Mode
(0VDD = 1.8V)
Sine Input, 3.5mA Mode
l
PDISS Power Dissipation
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l
30
57.4 TBD
149
200 TBD
29.6
57.1 TBD
121
172 TBD
29.3
mA
56.8 TBD
mA
104
mW
155 TBD mW
All Output Modes
PSLEEP Sleep Mode Power
1
1
1
mW
PNAP Nap Mode Power
10
10
10
mW
PDIFFCLK Power Increase with Differential Encode Mode Enabled
20
20
20
mW
(No Increase for Nap or Sleep Modes)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2142-12
LTC2141-12
LTC2140-12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS
Sampling Frequency (Note 10)
l1
65 1
40 1
25 MHz
tL
ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500
ns
tH
ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500
ns
Duty Cycle Stabilizer On l 2 7.69 500 2 12.5 500 2 20 500
ns
tAP
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
CONDITIONS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD
tC
tSKEW
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
CL = 5pF (Note 8)
CL = 5pF (Note 8)
tD – tC (Note 8)
Full Data Rate Mode
Double Data Rate Mode
MIN
TYP
MAX
UNITS
l
1.1
1.7
3.1
ns
l
1
1.4
2.6
ns
l
0
0.3
0.6
ns
6
Cycles
6.5
Cycles
21421012p
7

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