LH5164AZ8 Ver la hoja de datos (PDF) - Sharp Electronics

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LH5164AZ8

CMOS 64K (8K × 8) Static RAM

Sharp Electronics 

CMOS 64K (8K × 8) Static RAM

tWC

ADDRESS

CE1

tAW

tCW

(NOTE 2)

tCW

tWR (NOTE 4)

tWR

CE2

WE

DOUT

tAS

(NOTE 3)

(NOTE 6)

tWP

tWR

(NOTE 1)

tWZ

tOW

(NOTE 7)

tDW

tDH

(NOTE 5)

DIN

DATA VALID

NOTES:

1. The writing occurs during an overlapping period of CE1 = "LOW," CE2 = "HIGH," and WE = "LOW" (tWP).

2. tCW is defined as the time from the last occuring transit, either CE1 LOW transit or CE2 HIGH transit,

to the time when the writing is finished.

3. tAS is defined as the time from address change to writing start.

4. tWR is defined as the time from writing finish to address change.

5. The input signals of opposite phase to the outputs must not be applied while I/O pins are in the output state.

6. If CE1 LOW transit or CE2 HIGH transit occurs at the same time or after WE LOW transit, the output will

remain high-impedance.

7. If CE1 HIGH transit or CE2 LOW transit occurs at the same time or before WE HIGH transit, the output will

remain high-impedance.

Figure 5. OE Low Fixed

LH5164AZ8

5164AZ8-5

7

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