LH5164AZ8
CMOS 64K (8K × 8) Static RAM
tWC
ADDRESS
OE
tAW
tCW
(NOTE 2)
tWR
(NOTE 4)
CE1
tCW
tWR
CE2
tAS
(NOTE 3)
tWP
tWR
(NOTE 1)
WE
tOHZ
DOUT
tDW
tDH
(NOTE 5)
DIN
DATA VALID
NOTES:
1. The writing occurs during an overlapping period of CE1 = "LOW," CE2 = "HIGH," and WE = "LOW" (tWP).
2. tCW is defined as the time from the last occuring transit, either CE1 LOW transit or CE2 HIGH transit,
to the time when the writing is finished.
3. tAS is defined as the time from address change to writing start.
4. tWR is defined as the time from writing finish to address change.
5. The input signals of opposite phase to the outputs must not be applied while I/O pins are in the output state.
Figure 4. Write Cycle
5164AZ8-4
6