DP8051_07 Ver la hoja de datos (PDF) - Digital Core Design
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DP8051_07 Datasheet PDF : 10 Pages
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prgramdatai
prgdatao
prgramwr
prgaddr
prgromdata
DP8051CPU i
xdatai
xdatao
xaddr
xprgrd
xprgwr
8
8
12
On-chip Memory
(implemented as RAM)
0 Wait-State access
10
8
ASIC or FPGA
chip
On-chip Memory
(implemented as ROM)
0 Wait-State access
8
Off-chip Memory
16
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
ready
Wait-States
manager
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be imple-
mented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cy-
cles.
computed as {80C51 clock periods} divided by
{DP8051CPU clock periods} required to exe-
cute an identical function. More details are
available in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
9,00
9,00
9,00
12,00
9,00
9,00
9,00
12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DP8051CPU per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
Target
Clock
fre-
quency
Dhry/sec
(VAX MIPS)
80C51
-
12 MHz 268 (0.153)
80C310
-
33 MHz 1550 (0.882)
DP8051CPU STRATIX-II 150 MHz 26220 (14.924)
Core performance in terms of Dhrystones
PERFORMANCE
The following tables give a survey about the
Core area and performance in Programmable
Logic Devices after Place & Route (CPU fea-
tures and peripherals have been included):
Device
FLEX10KE
Speed grade
-1
Fmax
57 MHz
ACEX1K
-1
56 MHz
APEX20K
-1
50 MHz
APEX20KE
-1
68 MHz
APEX20KC
-7
79 MHz
APEX-II
-7
74 MHz
MERCURY
-5
101 MHz
CYCLONE
-6
93 MHz
CYCLONE-II
-6
95 MHz
STRATIX
-5
89 MHz
STRATIX-II
-3
160 MHz
Core performance in ALTERA® devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
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are trademarks of their respective owners.
27000
24000
21000
18000
15000
12000
9000
6000
3000
0
26220
268 1550
80C51 (12MHz)
DP8051CPU (150MHz)
80C310 (33MHz)
Area utilized by the each unit of DP8051CPU
core in vendor specific technologies is summa-
rized in table below.
Component
CPU*
Interrupt Controller
Power Management Unit
Area
[LC]
1640
100
10
[FFs]
285
40
5
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