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Fabricante

DP8051_07

Pipelined High Performance 8-bit Microcontroller

Digital Core Design 

SYMBOL

BLOCK DIAGRAM

prgromdata(7:0)

prgramdata(7:0)

xdatai(7:0)

ready

iprgromsize(2:0)

iprgramsize(2:0)

sxdmxdatai(7:0)

ramdatai(7:0)

sfrdatai(7:0)

prgaddr(15:0)

prgdatao(7:0)

prgramwr

xaddr(23:0)

xdatao(7:0)

xdataz

xprgrd

xprgwr

xdatard

xdatawr

sxdmadd(15:0)

sxdmdatao(7:0)

sxdmwe

sxdmoe

ramaddr(7:0)

ramdatao(7:0)

ramwe

ramoe

sfraddr(6:0)

int0

sfrdatao(7:0)

int1

sfroe

sfrwe

prgramdata(7:0)

prgromdata(7:0)

prgaddr(15:0)

prgdatao(7:0)

prgramwr

xaddr(23:0)

xdatao(7:0)

xdatai(7:0)

xdataz

ready

xprgrd

xprgwr

xdatard

xdatawr

Opcode

decoder

Program

memory

interface

External

memory

interface

iprgromsize(2:0)

iprgramsize(2:0)

ramaddr(7:0)

ramdatao(7:0)

ramdatai(7:0)

ramwe

ramoe

sfraddr(6:0)

sfrdatao(7:0)

sfrdatao(7:0)

sfroe

sfrwe

clk

reset

Control

Unit

Internal data

memory

interface

User SFR’s

interface

SXDM

interface

Interrupt

controller

sxdmaddr

sxdmdatao

sxdmdatai

sxdmoe

sxdmwe

int0

int1

Power

Manage-

ment Unit

DoCD™

Debug Unit

stop

pmm

tdi

tck

tms

tdo

rtck

coderun

debugacs

ALU

tdi

tck

tms

reset

clk

stop

pmm

tdo

rtck

coderun

debugacs

rsto

PINS DESCRIPTION

PIN

TYPE

DESCRIPTION

clk

reset

port0i[7:0]

port1i[7:0]

port2i[7:0]

port3i[7:0]

iprgramsize[2:0]

iprgromsize[2:0]

prgramdata[7:0]

prgromdata[7:0]

sxdmdatai[7:0]

xdatai[7:0]

ready

ramdatai[7:0]

sfrdatai[7:0]

int0

int1

tdi

tck

input Global clock

input Global reset

input Port 0 input

input Port 1 input

input Port 2 input

input Port 3 input

input Size of on-chip RAM CODE

input Size of on-chip ROM CODE

input Data bus from int. RAM prog. memory

input Data bus from int. ROM prog. memory

input Data bus from sync external data

memory (SXDM)

input Data bus from external memories

input External memory data ready

input Data bus from internal data memory

input Data bus from user SFR’s

input External interrupt 0

input External interrupt 1

input DoCD™ TAP data input

input DoCD™ TAP clock input

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are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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