DP8051XP_07 Ver la hoja de datos (PDF) - Digital Core Design

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DP8051XP_07

Pipelined High Performance 8-bit Microcontroller

Digital Core Design 

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design license allows using IP Core in

single FPGA bitstream and ASIC implementa-

tion. It also permits FPGA prototyping before

ASIC production.

Unlimited Designs license allows using IP Core

in unlimited number of FPGA bitstreams and

ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

● Single Design license for

○ VHDL, Verilog source code called HDL Sour-

ce

○ Encrypted, or plain text EDIF called Netlist

● Unlimited Designs license for

○ HDL Source

○ Netlist

● Upgrade from

○ Netlist to HDL Source

○ Single Design to Unlimited Designs

DESIGN FEATURES

♦ PROGRAM MEMORY:

The DP8051CPU soft core is dedicated

for operation with Internal and External Pro-

gram Memory. Internal Program Memory

can be implemented as:

○ ROM located in address range between

0x0000 ÷ (ROMsize-1)

○ RAM located in address range between

(RAMsize-1) ÷ 0xFFFF

External Program Memory can be im-

plemented as ROM or RAM located in ad-

dress range between ROMsize ÷ RAMsize.

♦ INTERNAL DATA MEMORY:

The DP8051CPU can address Internal

Data Memory of up to 256 bytes The Inter-

nal Data Memory can be implemented as

Single-Port synchronous RAM.

♦ EXTERNAL DATA MEMORY:

The DP8051CPU soft core can address

up to 16 MB of External Data Memory. Ex-

tra DPX (Data Pointer eXtended) register is

used for segments swapping.

♦ USER SPECIAL FUNCTION REGISTERS:

Up to 104 External (user) Special Func-

tion Registers (ESFRs) may be added to

the DP8051CPU design. ESFRs are mem-

ory mapped into Direct Memory between

addresses 0x80 and 0xFF in the same

manner as core SFRs and may occupy any

address that is not occupied by a core

SFR.

♦ WAIT STATES SUPPORT:

The DP8051CPU soft core is dedicated

for operation with wide range of Program

and Data memories. Slow Program and Ex-

ternal Data memory may assert a memory

Wait signal to hold up CPU activity.

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are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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