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KSZ8765CLX Ver la hoja de datos (PDF) - Microchip Technology

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KSZ8765CLX Datasheet PDF : 131 Pages
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KSZ8765CLX
TABLE 2-1: SIGNALS - KSZ8765CLX (CONTINUED)
Pin
Number
45
46
47
48
49
Pin
Name
RXD5_0
RXD5_1
GNDD
VDDIO
RXD5_2
50
RXD5_3
51
RXDV5/
CRSDV5/
RXD5_CTL
52
RXER5
53
CRS5
54
COL5
55
REFCLKO
56
PME_N
57
RXD5_4
58
RXD5_5
59
RXD5_6
60
RXD5_7
61
GNDD
Type
Note 2-1
Ipd/O
Ipd/O
GND
P
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
I/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
GND
Port
Description
5
GMII/RGMII/MII/RMII: Port 5 Switch receive Bit[0].
5
GMII/RGMII/MII/RMII: Port 5 Switch receive Bit[1].
— Digital Ground.
— 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
5
GMII/RGMII/MII: Port 5 Switch receive Bit[2].
RMII: No connection
5
GMII/RGMII/MII: Port 5 Switch receive Bit[3].
RMII: No connection
5
GMII/MII: RXDV5 is for Port 5 switch GMII/MII receive data
valid.
RMII: CRSDV5 is for Port 5 RMII carrier sense/receive data
valid output.
RGMII: RXD5_CTL is for Port 5 RGMII receive data control
5
GMII/MII: Port 5 Switch receive error.
RGMII/RMII: No connection.
5
GMII/MII: Port 5 Switch MII modes carrier sense.
RGMII/RMII: No connection.
5
GMII/MII: Port 5 Switch MII collision detect.
RGMII/RMII: No connection.
— 25 MHz Clock Output (Option)
Controlled by the strap pin LED2_0 and the Global Register 11
Bit[1]. Default is enabled; it is better to disable it if it’s not being
used.
— Power Management Event
This output signal indicates that a WoL event has been detected
as a result of a wake-up frame being detected. The KSZ8765-
CLX is requesting the system to wake up from low power mode.
Its assertion polarity is programmable with the default polarity to
be active-low.
5
GMII: Port 5 switch receive Bit[4].
RGMII/MI/RMII: No connection.
5
GMII: Port 5 switch receive Bit[5].
RGMII/MII/RMII: No connection.
5
GMII: Port 5 switch receive Bit[6].
RGMII/MII/RMII: No connection.
5
GMII: Port 5 switch receive Bit[7].
RGMII/MII/RMII: No connection.
— Digital Ground.
2016 Microchip Technology Inc.
DS00002130A-page 9

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