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KSZ8765CLX

Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces

Microchip Technology 

Option and Half-Duplex Back-Pressure Colli-

sion Flow Control

- IEEE 802.1w Rapid Spanning Tree Protocol

Support

- IGMP v1/v2/v3 Snooping for Multicast Packet

Filtering

- QoS/CoS Packets Prioritization Support:

802.1p, DiffServ-Based and Re-Mapping of

802.1p Priority Field Per Port Basis on Four

Priority Levels

- IPv4/IPv6 QoS Support

- IPV6 Multicast Listener Discovery (MLD)

Snooping

- Programmable Rate Limiting at the Ingress

and Egress Ports on a Per Port Basis

- Jitter-Free Per Packet Based Rate Limiting

Support

- Tail Tag Mode (1 byte Added before FCS)

Support on Port 5 to Inform the Processor

which Ingress Port Receives the Packet

- Broadcast Storm Protection with Percentage

Control (Global and Per Port Basis)

- 1K Entry Forwarding Table with 64 KB Frame

Buffer

- 4 Priority Queues with Dynamic Packet Map-

ping for IEEE 802.1P, IPV4 TOS (DIFF-

SERV), IPv6 Traffic Class, etc.

- Supports WoL Using AMD’s Magic Packet

- VLAN and Address Filtering

- Supports 802.1x Port-Based Security,

Authentication and MAC-Based Authentica-

tion via Access Control Lists (ACL)

- Provides Port-Based and Rule-Based ACLs

to Support Layer 2 MAC SA/DA Address,

Layer 3 IP Address and IP Mask, Layer 4

TCP/UDP Port Number, IP Protocol, TCP

Flag and Compensation for the Port Security

Filtering

- Ingress and Egress Rate Limit Based on Bit

per Second (bps) and Packet-Based Rate

Limiting (pps)

• Configuration Registers Access

- High-Speed SPI (4-Wire, up to 50 MHz) Inter-

face to Access All Internal Registers

- MII Management (MIIM, MDC/MDIO 2-Wire)

Interface to Access All PHY Registers per

Clause 22.2.4.5 of the IEEE 802.3 Specifica-

tion

- I/O Pin Strapping Facility to Set Certain Reg-

ister Bits from I/O Pins During Reset Time

- Control Registers Configurable On-the-Fly

KSZ8765CLX

• Power and Power Management

- Full-Chip Software Power-Down (All Register

Values are Not Saved and Strap-In value Will

Re-Strap after it Releases the Power-Down)

- Per-Port Software Power-Down

- Energy Detect Power-Down (EDPD), which

Disables the PHY Transceiver When Cables

are Removed

- Supports IEEE P802.3az Energy Efficient

Ethernet (EEE) to Reduce Power Consump-

tion in Transceivers in LPI State Even

Though Cables are Not Removed

- Dynamic Clock Tree Control to Reduce

Clocking in Areas that are Not in Use

- Low Power Consumption without Extra

Power Consumption on Transformers

- Voltages: Using External LDO Power Sup-

plies

- Analog VDDAT 3.3V or 2.5V

- VDDIO Support 3.3V, 2.5V, and 1.8V

- Low 1.2V Voltage for Analog and Digital Core

Power

- WoL Support with Configurable Packet Con-

trol

• Additional Features

- Single 25 MHz +50 ppm Reference Clock

Requirement

- Comprehensive Programmable Two-LED

Indicator Support for Link, Activity, Full-/Half-

Duplex, and 10/100 Speed

• Packaging and Environmental

- Commercial Temperature Range: 0°C to

+70°C

- Industrial Temperature Range: –40°C to

+85°C

- Package Available in an 80-Pin LQFP, Lead-

Free (RoHS-Compliant) Package

- Supports Human Body Model (HBM) ESD

Rating of 5 kV

- 0.065 µm CMOS Technology for Lower

Power Consumption

 2016 Microchip Technology Inc.

DS00002130A-page 2

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