NCP360SNT3G Ver la hoja de datos (PDF) - ON Semiconductor
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Fabricante
NCP360SNT3G
ON Semiconductor
NCP360SNT3G Datasheet PDF : 10 Pages
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NCP360
In Operation
NCP360 provides overvoltage protection for positive
voltage, up to 20ĂV. A PMOS FET protects the systems
(i.e.: VBUS) connected on the Vout pin, against positive
over-voltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built-in undervoltage lock out (UVLO)
circuit. During Vin positive going slope, the output remains
disconnected from input until Vin voltage is above 3.2ĂV
nominal. The FLAGV output is pulled to low as long as Vin
does not reach UVLO threshold. This circuit has a 50ĂmV
hysteresis to provide noise immunity to transient condition.
Vin (V)
20 V
OVLO
UVLO
0
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Internal PMOS FET
NCP360 includes an internal PMOS FET to protect the
systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
RDSon, during normal operation, will create low losses on
Vout pin, characterized by Vin versus Vout dropout. (See
Figure 16).
ESD Tests
NCP360 fully support the IEC61000-4-2, level 4 (Input
pin, 1 mF mounted on board).
That means, in Air condition, Vin has a ±15ĂkV ESD
protected input. In Contact condition, Vin has ±8ĂkV ESD
protected input.
Please refer to Fig 19 to see the IEC 61000-4-2
electrostatic discharge waveform.
Vout
OVLO
UVLO
0
Figure 18. Output Characteristic vs. Vin
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built-in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled until the input voltage exceeds OVLO -
Hysteresis.
FLAG output is tied to low until Vin is higher than
OVLO. This circuit has a 100ĂmV hysteresis to provide
noise immunity to transient conditions.
FLAG Output
NCP360 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded When Vin level recovers normal condition,
FLAG is held high. The pin is an open drain output, thus a
pull up resistor (typically 1 MW- Minimum 10 kW) must
be provided to Vbattery. FLAG pin is an open drain output.
Figure 19.
PCB Recommendations
The NCP360 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
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