5L35023 Ver la hoja de datos (PDF) - Integrated Device Technology

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Fabricante

5L35023

VersaClock® 3S Programmable Clock Generator

Integrated Device Technology 

5L35023 Datasheet

General AC Electrical Characteristics

VDD = 1.8V ±5%, TA = -40°C to +85°C; spread spectrum = off

Table 10. AC Electrical Characteristics

Symbol

Parameter

Conditions

Minimum Typical Maximum Units

fIN 1 Input Frequency

Input frequency limit (XIN).

8

Input frequency limit (LVCMOS to X1).

1

40

MHz

125

MHz

fOUT Output Frequency

Single-ended clock output limit (LVCMOS).

1

Differential clock output frequency (LPHCSL).

1

125

MHz

125

MHz

fVCO1 VCO Frequency Range of PLL1 VCO operating frequency range.

300

600

MHz

fVCO2 VCO Frequency Range of PLL2 VCO operating frequency range.

30

130

MHz

fVCO3 VCO Frequency Range of PLL3 VCO operating frequency range.

300

900

MHz

Cycle-to-cycle jitter (peak-to-peak), multiple

output frequencies switching, differential

outputs (1.8V nominal output voltage).

SE1 = 25MHz.

SE2 = 100MHz.

50

ps

SE3 = 125MHz.

DIFF1/2 = 100MHz.

tJ Clock Jitter

RMS phase jitter (12kHz to 20MHz integration

range) differential output, 1.8V nominal output

voltage.

25MHz crystal.

SE1=12.5MHz–REF/2.

SE2=133.333MHz–PLL3.

1.5

ps

SE3=120MHz–PLL1.

DIFF1/2=100MHz–PLL1.

REF=25M.

tSKEW Output Skew

tLOCK 2 Lock Time

Skew between the same frequencies, with

outputs using the same driver format.

PLL/DCO lock time.

75

ps

10

ms

1 Practical lower frequency is determined by loop filter settings.

2 Includes loading the configuration bits from OTP to PLL registers. It does not include OTP programming/write time.

3 Actual PLL lock time depends on the loop configuration.

©2017 Integrated Device Technology, Inc.

9

July 13, 2017

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