5L35023 Ver la hoja de datos (PDF) - Integrated Device Technology
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5L35023 Datasheet PDF : 38 Pages
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5L35023 Datasheet
Table 13. I2C Bus AC Characteristics
Symbol
Parameter
Conditions
Minimum
Typical Maximum Units
FSCLK
Serial Clock Frequency (SCL)
100
400
kHz
tBUF
Bus Free Time between STOP and START
1.3
μs
tSU:START Setup Time, START
0.6
μs
tHD:START Hold Time, START
0.6
μs
tSU:DATA
tHD:DATA
Setup Time, data input (SDA)
Hold Time, data input (SDA) 1
100
ns
0
μs
tOVD
Output Data Valid from Clock
0.9
μs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCL)
20 + 0.1 × CB
300
ns
tF
Fall Time, data and clock (SDA, SCL)
20 + 0.1 × CB
300
ns
tHIGH
High Time, clock (SCL)
0.6
μs
tLOW
Low Time, clock (SCL)
1.3
μs
tSU:STOP Setup Time, STOP
0.6
μs
1 A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
Glossary of Features
Table 14. Glossary of Features
Term
DFC
ORT
OE
SS
Slew Rate
PPS
Function Description
Dynamic Frequency Control; from selected PLL to support four VCO frequencies; means two different
output frequencies by assigned H/W pin state changes.
Overshot Reduction; when the DFC dynamic frequency change is functional, the VCO changes
frequencies smoothly to target frequency without overshoot or undershoot.
Output enable function; each output can be controlled by assigned OE pin and the dedicated OE pin can
be OTP programmable as global Power Down function (PD#) or Output Enable (OE) or Proactive Power
Saving function (PPS) or RESET pin function.
Spread spectrum clock.
LVCMOS outputs with slew rate control – slow and fast.
Proactive Power Saving; utilize OE pin as monitor pin for end device X2 clock status. See PPS Function
description for details.
Apply to
PLL2
PLL2
OE1–3
PLL1/PLL2
LVCMOS
SE1–3
©2017 Integrated Device Technology, Inc.
11
July 13, 2017
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