LT1767 Ver la hoja de datos (PDF) - Linear Technology

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Fabricante

LT1767

Monolithic 1.5A, 1.25MHz Step-Down Switching Regulators

Linear Technology 

LT1767/LT1767-1.8/

LT1767-2.5/LT1767-3.3/LT1767-5

APPLICATIONS INFORMATION

FB RESISTOR NETWORK

If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required, the

respective fixed option part, -1.8, -2.5, -3.3 or -5, should be

used. The FB pin is tied directly to the output; the necessary

resistive divider is already included on the part. For other

voltage outputs, the adjustable part should be used and an

external resistor divider added. The suggested resistor (R2)

from FB to ground is 10k. This reduces the contribution of

FB input bias current to output voltage to less than 0.25%.

The formula for the resistor (R1) from VOUT to FB is:

R1= R2 (VOUT −1.2)

1.2 −R2(0.25µA)

LT1767

ERROR

AMPLIFIER

gm

VSW

1.2V

FB

OUTPUT

R1

+

VC GND

R2

10k

1767 F02

Figure 2. Feedback Network

Input Voltage Range

The input voltage range for LT1767 applications depends

on the output voltage, the absolute maximum ratings of

the VIN and BOOST pins, and the operating frequency.

The minimum input voltage is determined by either the

LT1767’s minimum operating voltage of 2.73V or by its

maximum duty cycle. The duty cycle is the fraction of

time that the internal switch is on and is determined by

the input and output voltages:

DC = VOUT + VD

VIN – VSW + VD

where VD is the forward voltage drop of the catch diode

(~0.4V) and VSW is the voltage drop of the internal switch

(~0.4V at maximum load). This leads to a minimum input

voltage of:

VIN(MIN)

=

VOUT + VD

DCMAX

–

VD

+

VSW

with DCMAX = 0.80 at output current below 0.5A, and

DCMAX = 0.75 at higher loads. The maximum duty cycle

decreases when the LT1767 is synchronized to an external

clock; DCMAX = 1 – 0.25µs • fCLK.

The maximum input voltage is determined by the absolute

maximum ratings of the VIN and BOOST pins and by the

minimum duty cycle DCMIN = 0.16:

VIN(MAX )

=

VOUT + VD

DCMIN

–

VD

+

VSW

For a 12V input, the lowest practical output voltage is

1.8V. Minimum duty cycle will increase when the LT1767

is synchronized; DCMIN = 0.11µs • fCLK. Note that this is

a restriction on the operating input voltage; the circuit

will tolerate transient inputs up to the absolute maximum

ratings of the VIN and BOOST pins, provided the output

is not shorted.

For wider input voltage range, consult the related parts

table on the last page of this data sheet.

INPUT CAPACITOR

Step-down regulators draw current from the input supply in

pulses. The rise and fall times of these pulses are very fast.

The input capacitor is required to reduce the voltage ripple

this causes at the input of LT1767 and force the switching

current into a tight local loop, thereby minimizing EMI. The

RMS ripple current can be calculated from:

( ) / IRIPPLE(RMS) =IOUT VOUT VIN − VOUT VIN2

Higher value, lower cost ceramic capacitors are now available

in smaller case sizes. These are ideal for input bypassing

since their high frequency capacitive nature removes most

ripple current rating and turn-on surge problems. At higher

switching frequency, the energy storage requirement of the

1767fb

8

For more information www.linear.com/LT1767

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