AN-6067(2010_01) Ver la hoja de datos (PDF) - Fairchild Semiconductor

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AN-6067
(Rev.:2010_01)

Design and Application of Primary-Side Regulation (PSR) PWM Controller

Fairchild Semiconductor 

AN-6067

- Vfa + Ra

R1

VDD

VS

SGP100

VDD Cap. Vs Cap.

+

Vaux

-

R2

APPLICATION NOTE

Vin

+ Vf -

+

+

+

Vpri

Vsec

VO

-

-

−

na : np : 1

VO > Vsec

Figure 35. VDD and Snubber Capacitors Effect on Output Voltage

Reducing No-Load Output Voltage with a

“Dummy” Load

At no-load and very light load conditions, due to the very

low PWM frequency caused by feedback signal deviations

and output voltage rises, especially at low-line input voltage

condition. Increasing the addition of a dummy load can fix

this problem. Figure 36 shows the effect of a higher and

lower dummy load on the V-I curve. The level of the

dummy load is suggested at about 25~100mW.

Vo

lower snubber cap,

higher VDD cap , dummy load

higher snubber cap,

lower VDD cap , dummy load

Io

Figure 36. Dummy Load Effect on Output Characteristic

© 2008 Fairchild Semiconductor Corporation

Rev. 1.0.1 • 1/26/10

14

www.fairchildsemi.com

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