AN-6067(2010_01) Ver la hoja de datos (PDF) - Fairchild Semiconductor

Número de pieza

componentes Descripción

Fabricante

AN-6067
(Rev.:2010_01)

Design and Application of Primary-Side Regulation (PSR) PWM Controller

Fairchild Semiconductor 

AN-6067

Effect of the Vs Pin Capacitor

A VS capacitor with 22~68pF placed closely between Vs pin

and the GND pin is recommended. The capacitor is used to

bypass switching induced noise and keep the accuracy of the

sampled voltage. The value of the capacitor affects the load

regulation and constant current performance. Figure 31

illustrates the measured waveform on the Vs pin with a

different VS capacitor. If a higher value VS capacitor is used,

the charging time becomes longer and the sampled voltage is

higher than the actual value. Figure 32 shows the effect on

the sampled voltage with a different VS capacitor.

Figure 33 shows a measured Vs pin waveform at a no-load

condition. As illustrated, the feedback voltage is too narrow.

Additionally, a large VS capacitor causes the inaccurate

sampling of the voltage; resulting in the rising of the output

voltage. Figure 24 shows the influence of the VS capacitor

on the V-I curve.

No-Load

APPLICATION NOTE

VS Gate COMV Vf

Figure 33. Measured Vs Pin Waveform at No Load

Vo

Lower Vs Cap.

Higher Vs Cap.

Figure 31. Measured Waveform with

Different VS Capacitor

Vs pin waveform

higher Vs Cap

lower Vs Cap

sampling voltage

sampling voltage

No - Load

Figure 32. Effect on Sampling Voltage with

Different VS Capacitor

© 2008 Fairchild Semiconductor Corporation

Rev. 1.0.1 • 1/26/10

Io

Figure 34. Comparison of V-I Curve

with Different Vs Capacitor

Effect of VDD and Snubber Capacitors

VDD voltage and snubber capacitors are related to the

feedback signal inaccuracy and cause output voltage to rise

at no-load condition.

If the VDD capacitor is not big enough, the decreasing PWM

frequency at no-load condition causes VDD voltage to drop

quickly. In such a condition, the feedback signal is

dominated by the VDD voltage, but not the secondary output

voltage. To avoid this, it is recommended the VDD capacitor

value be larger than 4.7µF(6.8~10µF).

On the other hand, the value of the snubber capacitor also

affects the output voltage performance. When the MOSEFT

is turned off, the polarity of the transformer primary side

inductor is reversed and the energy stored in the transformer

inductor is delivered to the secondary to supply load current.

In the meantime, if the output voltage is higher than the

voltage on the secondary winding (Vsec), the output diode is

still reversed. The resulting voltage Vpri is then applied to

the primary inductor, Lp, which charges the snubber

capacitor. The charge time influences the feedback voltage

signal on the auxiliary winding. It is recommended that the

snubber capacitor remain under 472pF(332~102pF).

www.fairchildsemi.com

13

Share Link: