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5962D0153301QXC

16Megabit SRAM MCM

Aeroflex Corporation 

DQ0(0)

DQ1(0)

DQ2(0)

DQ3(0)

DQ4(0)

DQ5(0)

DQ6(0)

DQ7(0)

VSS

DQ0(1)

DQ1(1)

DQ2(1)

DQ3(1)

DQ4(1)

DQ5(1)

DQ6(1)

DQ7(1)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

60

59

58

57

Top View

56

55

54

53

52

51

50

49

48

47

46

45

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

DQ0(2)

DQ1(2)

DQ2(2)

DQ3(2)

DQ4(2)

DQ5(2)

DQ6(2)

DQ7(2)

VSS

DQ0(3)

DQ1(3)

DQ2(3)

DQ3(3)

DQ4(3)

DQ5(3)

DQ6(3)

DQ7(3)

Figure 2. 25ns SRAM Pinout (68)

PIN NAMES

A(18:0) Address

DQ(7:0) Data Input/Output

En

Device Enable

Wn WriteEnable

G Output Enable

VDD Power

VSS Ground

DEVICE OPERATION

Each die in the UT8Q512K32 has three control inputs called

Enable (En), Write Enable (Wn), and Output Enable (G); 19

address inputs, A(18:0); and eight bidirectional data lines,

DQ(7:0). The device enable (En) controls device selection,

active, and standby modes. Asserting En enables the device,

causes IDD to rise to its active value, and decodes the 19 address

inputs to each memory die by selecting the 2,048,000 byte of

memory. Wn controls read and write operations. During a read

cycle, G must be asserted to enable the outputs.

Table 1. Device Operation Truth Table

G Wn En I/O Mode Mode

X1

X

1 3-state

Standby

X

0

0 Data in Write

1

1

0 3-state

Read2

0

1

0 Data out Read

Notes:

1. “X” is defined as a “don’t care” condition.

2. Device active; outputs disabled.

READ CYCLE

A combination of Wn greater than V IH (min) withEn and G less

than VIL (max) defines a read cycle. Read access time is

measured from the latter of device enable, output enable, or valid

address to valid data output.

SRAM read Cycle 1, the Address Access is initiated by a change

in address inputs while the chip is enabled with G asserted and

Wn deasserted. Valid data appears on data outputs DQn(7:0)

after the specified tAVQV is satisfied. Outputs remain active

throughout the entire cycle. As long as device enable and output

enable are active, the address inputs may change at a rate equal

to the minimum read cycle time (tAVAV).

SRAM read Cycle 2, the Chip Enable-controlled Access is

initiated by En going active while G remains asserted, Wn

remains deasserted, and the addresses remain stable for the

entire cycle. After the specified tETQV is satisfied, the eight-bit

word addressed by A(18:0) is accessed and appears at the data

outputs DQn(7:0).

SRAM read Cycle 3, the Output Enable-controlled Access is

initiated by G going active while En is asserted, Wn is

deasserted, and the addresses are stable. Read access time is

tGLQV unless tAVQV or tETQV have not been satisfied.

2

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