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ISP1583

Hi-Speed USB peripheral controller

NXP Semiconductors. 

NXP Semiconductors

ISP1583

Hi-Speed USB peripheral controller

Table 3. Pin description …continued

Symbol[1] Pin

Type[2] Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

RW_N/ 19

J3

RD_N

F3

I

Read or write input — For the Freescale mode, this

function is determined by pin MODE0 = LOW during

power-up.

Read input — For the 8051 mode, this function is

determined by pin MODE0 = HIGH during power-up.

input pad; TTL; 5 V tolerant

DS_N/

20

K3

H3

I

Data selection input — For the Freescale mode, this

WR_N

function is determined by pin MODE0 = LOW at power-up.

Write input — For the 8051 mode, this function is

determined by pin MODE0 = HIGH at power-up.

input pad; TTL; 5 V tolerant

CS0_N[3] 21

J4

G3

O

chip selection output 0 for the ATA/ATAPI device; see

Table 61

CMOS output; 8 mA drive

CS1_N[3] 22

K4

F4

O

chip selection output 1 for the ATA/ATAPI device; see

Table 61

CMOS output; 8 mA drive

AD0

23

K5

G4

I/O bit 0 of the multiplexed address and data

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

AD1

24

J5

H4

I/O bit 1 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

AD2

25

K6

F5

I/O bit 2 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

VCC(I/O)[4] 26

J6

E5

-

I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16

AD3

27

K7

H5

I/O bit 3 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

AD4

28

J7

G5

I/O bit 4 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

AD5

29

K8

G6

I/O bit 5 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

AD6

30

J8

H6

I/O bit 6 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

AD7

31

K9

H7

I/O bit 7 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

VCC1V8[4] 32

K10

H8

-

voltage regulator output (1.8 V ± 0.15 V); tapped out

voltage from the internal regulator; this regulated voltage

cannot drive external devices; decouple this pin using a

0.1 µF capacitor; see Section 8.16

n.c.

33

-

-

-

not connected

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

© NXP B.V. 2008. All rights reserved.

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