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IDT71T024L150PZI

LOW POWER 2V CMOS SRAM 1 MEG (128K x 8-BIT)

Integrated Device Technology 

IDT71T024

LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ADDRESS

OE

CS1

t RC

t AA

t OE

t OLZ (5)

CS2

DATA OUT

t ACS(3)

t CLZ (5)

HIGH IMPEDANCE

t OHZ (5)

t CHZ (5)

DATAOUT VALID

3779 drw 06

TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)

tRC

ADDRESS

DATAOUT

tAA

tOH

PREVIOUS DATAOUT VALID

tOH

DATAOUT VALID

3779 drw 07

NOTES:

1. WE is HIGH for Read Cycle.

2. Device is continuously selected; CS1 is LOW and CS2 is HIGH.

3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

6

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