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IDT71T024L150PZI

LOW POWER 2V CMOS SRAM 1 MEG (128K x 8-BIT)

Integrated Device Technology 

IDT71T024

LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES

(VLC = 0.2V, VHC = VDD - 0.2V)

Symbol

Parameter

Test Condition

Min.

Typ. (1)

VDR

VCC for Data Retention

—

1.5

—

ICCDR

Data Retention Current

1) CS1 ≥ VHC and CS2 ≥ VHC

—

<1

tCDR(3)

Chip Deselect to Data

or

0

—

Retention Time

2) CS2 ≤ VLC

tR(3)

Operation Recovery Time

tRC(2)

—

NOTES:

1. TA = +25°C.

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization, but is not production tested.

Max.

Unit

—

V

5

µA

—

ns

—

ns

3779 tbl 09

LOW VDD DATA RETENTION WAVEFORM

VDD

1.8V

tCDR

CS

VIH

DATA

RETENTION

MODE

VDR ≥ 1.5V

VDR

1.8V

tR

VIH

3779 drw 05

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

AC Test Load

GND to VDD

3ns

VDD x 0.5

VDD x 0.5

See Figure 1

3779 tbl 10

AC TEST LOAD

DATAOUT

50pF*

VDD

3070Ω

3150Ω

*Including jig and scope capacitance.

3779 drw 04

Figure 1. AC Test Load

4

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