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LA76818

The BUS Control Functions of LA76818 (Tentative)

SANYO -> Panasonic 

Technical Note of LA76818

2002/01/23

The BUS Control Functions of LA76818 (Tentative)

Register Name

Bits General Description

T Disable

1 bits Disable the Test SW & enable Audio / Video Mute SW

This is a Test Mode Switch, which is used in IC production (in case of using IC tester

for measuring).

*If the bit of BUS is set as ‘0’, it becomes Test Mode. Then the test functions below will

take active.

• Vertical Test

• E/W Test

• Tint Test

• Color Test

• Drive Test

• Contrast Test

Also, audio / video is muted forcedly.

*Usually, this bit is set as ‘1’ when the television is operating normally.

AFC Gain & gate

1 Select horizontal first loop gain & H-sync gating on/off

This function is used for keeping the stability of H sync. signal when there is no input

signal or when a special VCR signal (VCR AGC Micro-vision) is input.

0

= Automatic mode

There is a gate signal for 1st AFC gain control and sync signal to protect them from

variety special signals and guarantee the stability of horizontal output in all our products

before. The level of the gain control can only be set as HIGH, MIDDLE & LOW.

When “no input signal” (conditions are: no V sync and ‘H LOCK’ is unlocked) is

detected, “LOW” mode will be set to keep the horizontal deflection stable so that the H

& V position of OSD will not be interrupted.

In addition, the improved operation of gain control and gating control in this IC

contribute to stabilize horizontal output of VCR signal in automatic mode.

1

= Enforce High Gain Mode (Gain = High, Gate = Non gate)

This mode is prior to pull-in operation, that’s why the stability is comparative weak.

This mode is used when tuning or some unexpected conditions.

H Freq.

6 Align ES Sample horizontal frequency

(MP is adjusted in the wafer line.)

Adjustment has done for mass production products. Although it’s no need any

adjustment at TV production line, set the register as “111111”. (But it needs adjustment

at engineering sample stage).

V Reset Timing

1

Select Vertical output start timing.

0

= Normal

1

=0.25H shifted

Select Vertical Reset Timing

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