MBM29LV800BA-120PFTR Ver la hoja de datos (PDF) - Fujitsu

Número de pieza

componentes Descripción

Fabricante

MBM29LV800BA-120PFTR

CMOS 8M (1M × 8/512K × 16) BIT

Fujitsu 

MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12

Table 8 MBM29LV800TA/BA Extended Command Definitions

Command

Sequence

Set to

Fast Mode

Fast

Program*1

Word

Byte

Word

Byte

Bus

Write

Cycles

Req'd

3

2

First Bus

Write Cycle

Addr Data

555H

AAAH

AAH

XXXH

A0H

XXXH

Second Bus

Write Cycle

Addr Data

2AAH

55H

555H

PA

PD

Third Bus

Write Cycle

Addr Data

555H

20H

AAAH

—

—

Fourth Bus

Read Cycle

Addr Data

—

—

—

—

Reset from Word

Fast Mode *1 Byte

2

XXXH

XXXH

90H

F0H*3

—

XXXH

XXXH

—

—

—

Extended

Word

Sector

Protect*2

4

XXXH 60H SPA 60H SPA 40H SPA

SD

Byte

SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).

SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected

sector addresses.

*1:This command is valid while Fast Mode.

*2:This command is valid while RESET=VID.

*3:This data "00H" is also acceptable.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the

read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover both

Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that

commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset

operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor

read cycles retrieve array data from the memory. The devices remain enabled for reads until the command

register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

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