CXB1456R Ver la hoja de datos (PDF) - Sony Semiconductor
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CXB1456R Datasheet PDF : 17 Pages
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CXB1456R
CLKPOL Pin Control
The CLKPOL pin is used to select the SFTCLK trigger edge. (See Table 8.)
The CLKPOL pin is open High-impedance TTL input, and this should not be left open for use. (See Fig. 12.
Recommended application circuit.)
Table 8. SFTCLK Polarity
CLKPOL
Receiver operation trigger
L
Rising edge
H
Falling edge
PANEL1 and 0 Pin Control
The PANEL1 and 0 pins are used to select the panel mode. (See Table 9.)
For the normal use, the all frequencies of SFTCLK (25MHz to 65MHz) can be covered by fixing both PANEL1
and 0 to High.
The PANEL1 and 0 pins are open High-impedance TTL inputs, and they should not be left open for use. (See
Fig. 12. Recommended application circuit.)
Table 9. Panel Mode
PANEL1 PANEL0 Supporting panel size
L
L
VGA (640 × 480)
L
H
SVGA (800 × 600)
H
L
XGA (1024 × 768)
H
H
VGA to XGA
Shift Clock
25MHz
40MHz
65MHz
25MHz to 65MHz
Serial rate
750Mbps
1200Mbps
1950Mbps
750Mbps to 1950Mbps
CE Pin Control
The CE pin is used to select the standby mode. (See Table 10.)
The CE pin is open High-impedance TTL input, and this should not be left open for use. (See Fig. 12.
Recommended application circuit.)
Table 10
CE
L
H
Operation mode
Standby mode, all TTL outputs fixed to Low (excluding LOS)
Normal mode
Test Pin Control
The TESTEXN and TESTDT pins are for test only. Select normal mode. (See Table 11.)
The TESTEXN and TESTDT pins are open High-impedance TTL inputs, and they should not be left open for use.
Table 11. Test mode
TESTEXN
L
H
TESTDT
X
X
Operation mode
Test mode
Normal mode
LOS Pin Output
The LOS pin shows the absence of proper level of SDATA signal. The LOS pin is High when the connector is
disconnected or the transmitter is idle.
The LOS pin is TTL output.
–9–
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