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M32171F3VFP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

2001-5-14 Rev.1.0

Mitsubishi Microcomputers

32171 Group

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

Outline of the CPU core

The M32171 Group uses the M32R RISC CPU core, and has

an instruction set which is common to all microcomputers in

the M32R family.

Instructions are processed in five pipelined stages consisting

of instruction fetch, decode, execution, memory access, and

write back. Thanks to its “out-of-order-completion” mechanism,

the M32R CPU allows for clock cycle efficient, instruction ex-

ecution control.

The M32R CPU internally has sixteen 32-bit general-purpose

registers. The instruction set consists of 83 discrete instruc-

tions, which come in either a 16-bit instruction or a 32-bit in-

struction format. Use of the 16-bit instruction format helps to

reduce the code size of a program. Also, the availability of 32-

bit instructions facilitates programming and increases the per-

formance at the same clock speed, as compared to

architectures with segmented address spaces.

Sum-of-products instructions comparable to DSP

The M32R CPU contains a multiplier/accumulator that can

execute 32 bits × 16 bits in one cycle. Therefore, it executes a

32 bit × 32 bit integer multiplication instruction in three cycles.

Also, the M32R CPU supports the following four sum-of-prod-

ucts instructions (or multiplication instructions) for DSP func-

tion use.

(1) 16 high-order register bits × 16 high-order register bits

(2) 16 low-order register bits × 16 low-order register bits

(3) All 32 register bits × 16 high-order register bits

(4) All 32 register bits × 16 low-order register bits

Furthermore, the M32R CPU has instructions for rounding the

value stored in the accumulator to 16 or 32 bits, and instruc-

tions for shifting the accumulator value to adjust digits before

storing in a register. Because these instructions also can be

executed in one cycle, DSP comparable data processing ca-

pability can be obtained by using them in combination with

high-speed data transfer instructions such as Load & Address

Update or Store & Address Update.

Address space

The M32171 Group’s logical addresses are always handled in

32 bits, providing 4 Gbytes of linear address space. The

M32171 Group’s address space consists of the following.

User space

A 2-Gbyte area from H’0000 0000 to H’7FFF FFFF is the user

space. Located in this space are the user ROM area, external

extended area, internal RAM area, and SFR (Special Func-

tion Register) area (internal peripheral I/O registers). Of

these, the user ROM area and external extended area are lo-

cated differently depending on mode settings.

Boot program space

A 1-Gbyte area from H’8000 0000 to H’BFFF FFFF is the boot

program area. This space contains the on-board program-

ming program (boot program) used in blank state by the inter-

nal flash memory.

System space

A 1-Gbyte area from H’C000 0000 to H’FFFF FFFF is the

system area. This space is reserved for use by development

tools such as an in-circuit emulator and debug monitor, and

cannot be used by the user.

Three operation modes

The M32170 and M32174 Group has three operation modes:

single-chip mode, external extended mode, and processor

mode. These operation modes are changed from one to an-

other by setting the MOD0 and MOD1 pins.

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