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M32171F3VFP

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

2001-5-14 Rev.1.0

Mitsubishi Microcomputers

32171 Group

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER

Table 2 Outline Performance (1/2)

Functional Block

M32R CPU core

Features

M32R family CPU core, internally configured in 32 bits

Built-in multiplier-accumulator (32 × 16 + 56)

Basic bus cycle : 25 ns (CPU clock frequency at 40 MHz, Internal peripheral clock frequency at 20 MHz)

Logical address space : 4G bytes, linear

General-purpose register : 32-bit register × 16, Control register: 32-bit register × 5

accumulator : 56 bits

External data bus

16 bits data bus

Instruction set

16-bit/32-bit instruction formats

83 instructions/ 9 addressing modes

Internal flash memory

M32171F4VFP : 512K bytes

M32171F3VFP : 384K bytes

M32171F2VFP : 256K bytes

Rewrite durability : 100 times

Internal RAM

DMAC

16K bytes

10 channels (DMA transfers between internal peripheral I/Os, between internal

peripheral I/O and internal RAM, and between internal RAMs)

Channels can be cascaded and can operate in combination with internal peripheral I/O

Multijunction timer

37 channels of multijunction timers

• 16-bit output-related timers × 11 channels (single-shot, delayed single-shot)

• 16-bit input/output-related timers × 10 channels (event count mode, single-shot, PWM, measurement)

• 16-bit input-related timers × 8 channels (measurement, event count mode)

• 32-bit input-related timers × 8 channels (measurement)

Flexible timer configuration is possible through interconnection of channels using the event bus.

A-D converter

10-bit multifunction A-D converters

• Input 16 channels

• Scan-based conversion can be switched with 4, 8, and 16

• Capable of interrupt conversion during scan

• 8-bit/10-bit readout function available

Serial I/O

3 channels (The serial I/Os can be set for synchronous serial I/O or UART.

SIO2 is UART mode only)

Real-time debugger (RTD)

1-channels dedicated clock-synchronized serial

• The entire internal RAM can be read or rewritten from the outside without CPU intervention

Interrupt controller

Controls interrupts from internal peripheral I/Os

(Priority can be set to one of 8 levels including interrupt disabled)

Wait controller

Controls wait when accessing external extended area

(1 to 4 wait cycles inserted + prolonged by external WAIT signal input)

CAN

16-channels message slots

JTAG

Boundary-Scan function

4

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