BR93LC46 Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93LC46 Datasheet PDF : 12 Pages
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Memory ICs
BR93LC46 / BR93LC46F / BR93LC46RF / BR93LC46FV
CS
1
2
4
SK
9
10
tCS
STATUS
25
DI
1
DO
High Z
0
1
A5 A4
A1 A0 D15 D14
Fig. 4 Write cycle timing (WRITE)
CS
1
2
5
10
SK
D1 D0
tSV
BUSY READY
tE / W
tSV
STATUS
25
DI
1
0
0
0
1
D15 D14
D1 D0
DO
High Z
tCS
BUSY READY
tE / W
Fig. 5 Write all address cycle timing. (WRAL)
(STATUS)
(7) All address write (Figure 5)
After time tCS following the fall of CS, after input of the
write command), if CS is set to HIGH, the write execute
With this command, the input 16-bit data is written
simultaneously to all of the addresses (64 words).
= BUSY (LOW) and the command wait status READY
Rather than writing one word at a time, in succession,
(HIGH) are output.
data is written all at one time, enabling a write time of
If in the command wait status (STATUS = READY), the
next command can be performed within the time tE / W.
Thus, if data is input via SK and DI with CS = HIGH in
tE / W.
(8) Write disable (Figure 6)
When the power supply is turned on, the IC enters the
the tE / W period, erroneous operations may be per-
formed. To avoid this, make sure that DI = LOW when
write disable status. Similarly, when the write disable
command is issued, the IC enters the same status.
CS = HIGH. (Caution is especially important when
When in this status, all write commands are ignored,
common input ports are used.) This applies to all of the
but read commands may be executed.
write commands.
In the write enable status, writing begins even if a write
command is entered accidentally. To prevent errors of
this type, we recommend executing a write disable
command after writing has been completed.
CS
SK
DI
1
0
0
0
0
DO
High Z
Fig. 6 Write disable cycle timing (WDS)
8
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