PD5036 Ver la hoja de datos (PDF) - Unspecified

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Fabricante

PD5036

TELEPHONE RING GENERATOR CONTROLLER

Unspecified 

FREQUENCY SELECTION

F0, F1: Selection of a single output ringing frequency between the four

available options of 16.7, 20, 25 or 50Hz is achieved by the F0 and F1

inputs.

The st ate of F0 and F1 input s m ust be set and stable prior to

powering the P D5036. Changi ng the i nput state while the PD5036

is operating may not ef fect t he out put f requency, and m ay cause

the controller to become unstable state.

The f requency s election s hould be m ade according to the OUTPUT

RINGING & PWM FREQUENCIES table on page 45.

These i nputs are CM OS s tandard and can be driven directly from

CMOS c omponents, or t he f requency s election c an be ac hieved by

tying them to GND or Vcc.

Note: The P D5036 operat ion m ay be af fected by excessive n oise

surges on F0 and F1 terminals while operating.

VCC

F1 3

100K

VCC

F0 4

100K

PD5036

TELEPHONE RING GENERATOR CONTROLLER

CAD_In: Thi s i nput l ine s hould be c onnected t o t he out put of t he A /D

circuit’s external comparator. CAD_In = “1” will increase the PW M duty

cycle a t th e PAD _Out lin e. C AD_In = “ 0” w ill d ecrease th e PW M duty

cycle at the PAD_Out line. When the sampled voltage is stable, the A/D

PWM duty cycle will change up and dow n by 1 bit and t he comparator

output will vibrate. These 1-bit vibrations are ignored by the A/D.

Applications that use highly regulated power supplies may eliminate the

A/D external portions. In this event, the CAD_In should be permanently

connected to GND. Note that no out put vol tage regul ations bas ed on

input voltage changes will be performed.

LOW PASS NETWORK

The network is connected between the PAD_Out and the negative input

of the comparator, built from R3 & C1.

The low pass network is designed to average the PWM signal into a DC

Level. This DC level is compared to the sampled voltage.

It is recommended to calculate t he Low P ass net work c omponents

values according to the following:

τ(Recommended) = C1 • R3 = 89.1mS @ 96KHz Operation

τ(Recommended) = C1 • R3 = 52mS @ 307KHz Operation

* For timing details refer to A/D CONVERTER, INTERNAL

FUNCTIONAL PARAMETERS TABLE.

Vin

Frequency Selection Inputs

LINE REGULATION (A/D UNIT)

The ri ng generat or c ircuit des ign i s bas ed on an open loop flyback

topology. In order t o regul ate t he out put f or i nput vol tage c hanges, a

forward compensation mechanism is used.

This m echanism i s bas ed on a di gital s ampling of t he i nput vol tage by

the A/D unit, and c orrection of t he m ain P WM dut y c ycle ac cording t o

the internal transfer function.

The input voltage is sampled by an 8bi t A/D unit, which is composed of

external analog components and the internal PD5036 logic.

The internal portion of the A/D generates a PWM signal (PAD_Out) with

a changing duty cycle according to the voltage sampled by the CAD_In

terminal.

The s ampled i nput vol tage i nformation i nfluences the ringer output

voltage amplitude in s uch a w ay t hat c hanges i n V in generates onl y a

small change in Vout.

PAD_Out: P WM out put f or t he ex ternal A /D c ircuit. The P WM

frequency is the oscillator frequency divided by 8.

This line is connected to an external Low pass network that averages

the PWM pulses to a DC voltage. The level of this DC voltage is

proportional to the duty cycle of the PWM signal. The Low pass network

is connected to the negative input of an external comparator. This DC

voltage tracks the sampled voltage that is connected to the positive

input of the comparator. If the DC voltage is lower than the sampled

voltage, the internal A/D circuit will increase the PWM duty cycle. This

will increase the DC level. The opposite happens when the sampled

voltage is lower than the DC voltage.

R1

Vsample

R2

3+

2-

C1

PD5019

1

CMP_IN

R3

PAD_OUT

INTERNAL

A/D

8Bit Data to Transfer

Function

A/D Circuit Implementation

• The comparator inputs for the A/D function must operate in the

range of 0 to 5V.

• The Vsample sampling is synchronized for the sine wave peak.

Voltage Di vider: The voltage di vider c onnects t o t he pos itive i nput of

the comparator and is built of R1 & R2.

The voltage divider is required when an i nput voltage, V in, higher than

5V is used. Design the V sample vol tage di vider t o del iver 2. 5V f or

typical Vin Value is recommended.

OUTPUT PROTECTION MECHANISM

The overload and short c ircuit prot ection m echanisms s upport t hree

protection levels:

1. Immediate pulse by pulse, input current limiting.

2. Power reduction, by output amplitude reduction.

3. Shut down for limited periods, to reduce heat dissipation.

The i nput of t he prot ection uni t i s t he CL i nput, c onnected to external

current sense circuit output.

CL - Current Limiting Pulse Counter:

When the CL input changes to a Low due to excessive switch current,

the PWM output immediately changes to Low until the end of the

current PWM cycle. This will terminate the current through the switching

FET and the CL input will return to a high level.

PowerDsine Ltd. Tel: +972-3-934-7663 • Fax: +972-3-934-7669 • Email: sales@powerdsine.com

PowerDsine Inc. Tel: +516-756-4680 • Fax: +516-756-4691• Email: pwrdsine@erols.com

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