PD5036 Ver la hoja de datos (PDF) - Unspecified
Número de pieza
componentes Descripción
Fabricante
PD5036 Datasheet PDF : 14 Pages
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DETAILED DESCRIPTION
CLOCK
XTAL1, XT AL2: The oscillator generates t he int ernal P D5036 c lock
frequency.
A Crystal, Ceramic Resonator, or an external clock source may be used
to generate the clock’s basic frequency.
When a Crystal or a Ceramic Resonator is used, it should be connected
between XTAL1 and XTAL2 t erminal. For an ex ternal c lock s ource,
connect the source to XTAL1, leaving XTAL2 unconnected.
When us ing a Ceram ic Res onator, us e t he produc t’s specification
connection recommendations.
When using a Crystal or Ceramic Resonator, a 1Mohm 1% bias resistor
must be connected in parallel.
C1 and C2 recommended values for the different frequency sources are
specified in the table below.
Oscillator type
Frequency
C1
C2
Crystal 12.
28MHz
22pF
22pF
Crystal 19.
66MHz
10pF
10pF
Ceramic Resonator
12.28MHz
10pF
56pF
Ceramic Resonator
19.66MHz
10pF
When us ing an ex ternal c lock s ource, C1 and C2 and t
should not be installed and XTAL2 should be left open.
56pF
he Res istor
For t he os cillator f requency, refer t o t he OUTP UT RI NGING & PWM
FREQUENCIES Table.
1MΩ
1%
XTAL1 6
PD5036
TELEPHONE RING GENERATOR CONTROLLER
VCC
Inhibit
signal
4.7K
C3
Inhibit
VCC
1
100K
C4
FS 2
100K
100KHz PWM Output POR Configuration
The v alue of C3 and C4 w ill be det ermined ac cording t o the Supply
Voltage Rise Time and the Inhibit delay operation.
When us ing a 100K Hz P WM out put c onfiguration t he val ue of C4
should be 20 times smaller than C3.
[τ (FS) < τ (Inhibit)].
VCC
Inhibit
signal
C3
4.7K
VCC
1
100K
FS
2
100K
XTAL2 7
C2
C1
Oscillator Typical Configuration
TURN ON RESET OF THE PD5036
For proper operat ion, t he P D5036 c ontroller must be reset after power
is appl ied. Res et i s perf ormed by s etting t he I nhibit and t he FS
terminals to a high logic level for longer than 1µ sec.
The Inhibit and the FS t erminals are c onnected t o an i nternal S chmitt
input buffer with an internal 100KOhm pull down resistor.
To enable Power On Reset (POR) and proper inhibit operation, a series
resistor and pull up capacitors m ust be c onnected t o t he I NHIBIT
terminal. The val ue of the resistor and t he pull up capacitors determine
the reset duration, and delay of the inhibit operation.
300KHz PWM Output POR Configuration
INHIBIT: The Inhibit i nput s erves t o turn the device’s output On/Off by
using digital control levels.
High logic level (“1”) disables the device’s output.
When the 96KHz configuration is utilized (FS=”0”), the Inhibit shut down
response is internally del ayed unt il t he end of t he c urrent hal f s ine
cycle, to the nearest output zero crossing.
When t he 307K Hz c onfiguration is ut ilized (FS =”1”), t he Inhibit shut
down response is immediate.
FS: This l ine s elects bet ween 96K Hz and 307KHz main PWM
frequency.
FS= ”0” = 96KHz
FS= ”1” = 307KHz
The 96K Hz P WM f requency i s s uitable f or m edium pow er sine wave
generators, with synchronous switching at the secondary.
In low cost, low pow er, ri ng generat or appl ications, t he s ynchronous
switching circuitry may be el iminated. I n order t o m aintain reas onable
efficiency w hile not em ploying s ynchronous switching, the 307KHz
PWM frequency is employed.
PD5036
US Patent No. 5,828,558
Patent Pending in Europe and Asia
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