AT17LV256-10CI Ver la hoja de datos (PDF) - Atmel Corporation

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AT17LV256-10CI

FPGA Configuration EEPROM Memory

Atmel Corporation 

Table 1-1. AT17LV Series Packages

Package

8-lead LAP

AT17LV65/

AT17LV128/

AT17LV256

Yes

AT17LV512/

AT17LV010

Yes

AT17LV002

Yes

AT17LV040

(3)

8-lead PDIP

Yes

Yes

–

–

8-lead SOIC

Yes

Use 8-lead

LAP(1)

Use 8-lead

LAP(1)

(3)

20-lead PLCC

Yes

Yes

Yes

–

20-lead SOIC

Yes(2)

Yes(2)

Yes(2)

–

44-lead TQFP

–

–

Yes

Yes

Notes:

1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC

package is not available for the AT17LV512/010/002 devices, it is possible to use an 8-lead

LAP package instead.

2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the

AT17LV512/010/002 devices.

3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.

2. Pin Configuration

Figure 2-1. 8-lead LAP

DATA 1

CLK 2

(WP(1)) RESET/OE 3

CE 4

8 VCC

7 SER_EN

6 CEO (A2)

5 GND

Figure 2-2. 8-lead SOIC

DATA 1

CLK 2

(WP(1)) RESET/OE 3

CE 4

8 VCC

7 SER_EN

6 CEO (A2)

5 GND

Figure 2-3. 8-lead PDIP

DATA 1

CLK 2

(WP(1)) RESET/OE 3

CE 4

8 VCC

7 SER_EN

6 CEO (A2)

5 GND

2 AT17LV65/128/256/512/010/002/040

2321I–CNFG–2/08

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