AT17LV256-10NC Ver la hoja de datos (PDF) - Atmel Corporation
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AT17LV256-10NC Datasheet PDF : 14 Pages
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Block Diagram
POWER ON
RESET
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power-up, or on command, depending on the state of the
FPGA mode pins. In Master Mode, the FPGA automatically
loads the configuration program from an external memory.
The AT17 Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
This document discusses the AT6000 FPGA interface. For
more details or AT40K FPGA applications, please refer-
ence “AT6000 Series Configuration” or “AT40K Series
Configuration” application notes.
Controlling the Low-density AT17
Series Serial EEPROMs During
Configuration
Most connections between the FPGA device and the AT17
Serial EEPROM are simple and self-explanatory.
• The DATA output of the AT17 Series Configurator drives
DIN of the FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17 Series Configurator.
• The CEO output of any AT17C/LV128/256 drives the CE
input of the next AT17C/LV128/256 in a cascade chain of
EEPROMs. An AT17C/LV65 can only be used at the end
of a cascade chain or as a standalone device.
• SER_EN must be connected to VCC (except
during ISP).
There are two different ways to use the inputs CE and OE.
Condition 1
The simplest connection is to have the FPGA CON pin
drive both CE and RESET/OE(1) in parallel (Figure 1). Due
to its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
Configurator does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Note: 1. For this condition, the reset polarity of the EEPROM
must be set active High.
2
AT17C/LV65/128/256
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