M5M5V208AKV-70L Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
Número de pieza
componentes Descripción
Fabricante
M5M5V208AKV-70L Datasheet PDF : 8 Pages
| |||
Revision-A0.2E 29.Jan.'99
M5M5V208AKV/KR
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( S1 control mode)
A0~17
S1
tsu (A)
S2
(Note 3)
(Note 5)
W
(Note 3)
DQ1~8
Write cycle (S2 control mode)
A0~17
tCW
tsu (S1)
trec (W)
(Note 4)
tsu (D) th (D)
DATA IN
STABLE
tCW
(Note 3)
(Note 3)
S1
S2
W
DQ1~8
(Note 3)
tsu (A)
tsu (S2)
trec (W)
(Note 3)
(Note 5)
(Note 3)
(Note 4)
tsu (D)
th (D)
(Note 3)
DATA IN
STABLE
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2 high overlaps S1 and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
MITSUBISHI ELECTRIC
6
Share Link: 