QL8X12B-0PF100C Ver la hoja de datos (PDF) - QuickLogic Corporation

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QL8X12B-0PF100C

pASIC 1 Family Very-High-Speed CMOS FPGA

QuickLogic Corporation 

pASIC

HIGHLIGHTS

…1,000

usable ASIC gates,

64 I/O pins

QL8X12B

pASIC® 1 Family

Very-High-Speed CMOS FPGA

Rev B

Very High Speed – ViaLink® metal-to-metal programmable–via

antifuse technology, allows counter speeds over 150 MHz and logic

cell delays of under 2 ns.

High Usable Density – An 8-by-12 array of 96 logic cells provides

1,000 usable ASIC gates (2,000 PLD gates) in 44-pin and 68-pin

PLCC, and 100-pin TQFP packages.

Low-Power, High-Output Drive – Standby current typically 2 mA.

A 16-bit counter operating at 100 MHz consumes less than 50 mA.

Minimum IOL of 12 mA and IOH of 8 mA

Low-Cost, Easy-to-Use Design Tools – Designs entered and

simulated using QuickLogic's new QuickWorks® development

4

environment, or with third-party CAE tools including Viewlogic,

Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place

and route on PC and workstation platforms using QuickLogic

software.

QL8x12B

Block Diagram

96 Logic Cells

= Up to 56 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells

4-5

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