DS1204V Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS1204V

Electronic Key

Dallas Semiconductor -> Maxim Integrated 

DS1204V

register on each low-to-high transition of the CLK input.

The command register must match the exact bit pattern

that defines normal operation for read or write, or com-

munications are ignored. If the command register is

loaded properly, communications are allowed to contin-

ue. The next 64 cycles to the key are reads. Data is

clocked out of the key on the high-to-low transition of the

clock from the identification memory. Next, 64 write

cycles must be written to the compare register. These

BLOCK DIAGRAM - NORMAL MODE Figure 1

D/Q

64 bits must match the exact pattern stored in the secu-

rity match memory. If a match is not found, access to ad-

ditional information is denied. Instead, random data is

output for the next 128 cycles when reading data. If write

cycles are being executed, the write cycles are ignored.

If a match is found, access is permitted to a 128-bit read/

write nonvolatile memory. Figure 2 is a summary of nor-

mal mode operation and Figure 3 is a flow chart of the

normal mode sequence.

CLK

RST

CONTROL

LOGIC

64–BIT

IDENTIFICATION

64–BIT

SECURITY MATCH

COMPARE REGISTER

COMMAND REGISTER

128–BIT

SECURE MEMORY

SEQUENCE - NORMAL MODE Figure 2

PROTOCOL

IDENTIFICATION

COMMAND WORD

64 READ CYCLES

MATCH

SECURE MEMORY

128 READ OR WRITES

RANDOM DATA

SECURITY MATCH

64 WRITE CYCLES

021798 2/10

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