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SDA2586-5

Nonvolatile Memory 8-Kbit E2PROM with I2C Bus Interface

Siemens AG 

SDA 2586-5

Control Functions of the I2C Bus

The device is controlled by the controller (master) via the I2C Bus in two operating modes: read

cycle, and reprogramming cycle, including erase and write to a memory address. In both operating

modes, the controller, as transmitter, has to provide 3 bytes to the bus after the start condition. Each

byte has to be followed by an acknowledge bit. During a memory read, at least eight additional clock

pulses are required to accept the data from the memory, before the stop condition may follow. In the

programming instance, the active programming process is only started by the stop condition after

data input, see figure 3.

The chip select word includes the chip select bit CS. Thus it is possible to parallel two memory

devices. Chip select is obtained when the control bits logically correspond to the condition selected

at the select input CS. The two most significant bits A8 and A9 are inputs with the chip select words

CS/E.

Checking the End of the Programming Cycle and Breaking off the Programming Cycle

Addressing the chip by the input of CS/E during active reprogramming terminates the programming

cycle. If the chip is addressed by entering CS/A, this will be ignored. Only when the programming

cycle has terminated will the chip react on CS/A. With this procedure the end of the programming

cycle can be checked, see figure 3.

Memory Read

After the input of the two control words CS/E and WA, the resetting of the start condition and the

input of a third control word CS/A, the memory is set ready to read. During acknowledge clock No. 9,

the memory information is transferred in parallel to the internal data register. Subsequent to the

falling edge of the acknowledge clock the data output is low-impedance and the first data bit can be

sampled, see figure 4. With each shift clock, an additional bit reaches the output. After reading a

byte, the internal address counter is automatically incremented through the master receiver

acknowledge, so that any number of memory locations can be read one after the other. At address

1024, an overflow to address 0 is initiated. With the stop condition, the data output returns to high-

impedance mode. The internal sequence control of the memory component is reset from the read

to the quiescent state with the stop condition.

Semiconductor Group

42

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