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SDA2586-5 Datasheet PDF : 12 Pages
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Nonvolatile Memory 8-Kbit E2PROM
with I2C Bus Interface
SDA 2586-5
Preliminary Data
MOS IC
Features
q Word-organized, reprogrammable nonvolatile memory in
n-channel floating-gate technology (E2PROM)
q 1024 × 8-bit organization
q Supply voltage 5 V
q Serial 2-line bus for data input and output (I2C Bus)
q Reprogramming mode, 10 ms erase / write cycle
q Reprogramming by means of on-chip control
(without external control)
q The end of the programming cycle can be checked
q Data retention in excess of 10 years
q More than 104 reprogramming cycles per address
P-DIP-8-1
Type
SDA 2586-5
Ordering Code
Q67100-H5101
Package
P-DIP-8-1
Circuit Description
I2C Bus Interface
The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a data line SDA and a clock line SCL. The data line require an external pull-up resistor
to VCC (open drain output stages).
The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stages are disabled. As long as SCL remains "1",
information changes on the data bus indicate the start or the end of a data transfer between two
components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1"
a stop condition. During a data transfer, the information on the data bus will only change when the
clock line SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I2C Bus system, the device can operate as a receiver, and as a transmitter
(slave receiver/listener, or slave transmitter/talker). Between a start and a stop condition, the
information is always transmitted in byte-organized form. Between the falling edge of the eighth
transmission pulse and a ninth acknowledge clock pulse, the device sets the SDA-line to low as a
reception confirmation, if the chip select conditions have been met. During the output of data, the
data output of the memory becomes high in impedance during the ninth clock pulse (acknowledge
master).
The signal timing required for the operation of the I2C Bus is summarized in figure 2.
Semiconductor Group
41
07.94
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