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FT232BQ Datasheet PDF : 26 Pages
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FT232BQ USB UART ( USB - Serial) I.C.
• Programmable Receive Buffer Timeout
to the device and they will be sequentially sent to
In the previous device, the receive buffer timeout
the interface at a rate controlled by the prescaler
used to flush remaining data from the receive
setting. As well as allowing the device to be used
buffer was fixed at 16ms timeout. This timeout is
stand-alone as a general purpose IO controller for
now programmable over USB in 1ms increments
example controlling lights, relays and switches,
from 1ms to 255ms, thus allowing the device to
some other interesting possibilities exist. For
be better optimised for protocols requiring faster
instance, it may be possible to connect the device
response times from short data packets.
to an SRAM configurable FPGA as supplied by
vendors such as Altera and Xilinx. The FPGA
• TXDEN Timing fix
device would normally be un-configured (i.e. have
TXDEN timing has now been fixed to remove the
no defined function) at power-up. Application
external delay that was previously required for
software on the PC could use Bit Bang Mode to
RS485 applications at high baud rates. TXDEN
download configuration data to the FPGA which
now works correctly during a transmit send-break
would define its hardware function, then after the
condition.
FPGA device is configured the FT232BQ can
switch back into UART interface mode to allow
• Relaxed VCC Decoupling
the programmed FPGA device to communicate
The 2nd generation devices now incorporate a level
with the PC over USB. This approach allows a
of on-chip VCC decoupling. Though this does
customer to create a “generic” USB peripheral
not eliminate the need for external decoupling
who’s hardware function can be defined under
capacitors, it significantly improves the ease of
control of the application software. The FPGA
PCB design requirements to meet FCC, CE and
based hardware can be easily upgraded or
other EMI related specifications.
totally changed simply by changing the FPGA
configuration data file. Application notes, software
• Improved PreScaler Granularity
and development modules for this application area
The previous version of the Prescaler supported
will be available from FTDI and other 3rd parties.
division by (n + 0), (n + 0.125), (n + 0.25) and
(n + 0.5) where n is an integer between 2 and
16,384 (214). To this we have added (n + 0.375),
• PreScaler Divide By 1 Fix
The previous device had a problem when the
(n + 0.625), (n + 0.75) and (n+ 0.875) which can
integer part of the divisor was set to 1. In the 2nd
be used to improve the accuracy of some baud
generation device setting the prescaler value to 1
rates and generate new baud rates which were
gives a baud rate of 2 million baud and setting it
previously impossible (especially with higher baud
to zero gives a baud rate of 3 million baud. Non-
rates).
integer division is not supported with divisor values
of 0 and 1.
• Bit Bang Mode
The 2nd generation device has a new option
referred to as “Bit Bang” mode. In Bit Bang mode,
the eight UART interface control lines can be
switched between UART interface mode and an
8-bit Parallel IO port. Data packets can be sent
DS232BQ Version 1.8 © Future Technology Devices Intl. Ltd. 2005
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