S3C70F2 Ver la hoja de datos (PDF) - Samsung
Número de pieza
componentes Descripción
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S3C70F2 Datasheet PDF : 38 Pages
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PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN DESCRIPTIONS
Table 1-1. S3C70F2/C70F4 Pin Descriptions
Pin Name
P0.0
P0.1
P0.2
P1.0
P1.1
P2.0–P2.3
P3.0
P3.1
P3.2
P4.0–P4.3
P5.0–P5.3
P6.0
P6.1
P6.2
P6.3
INT0
INT1
CIN0–CIN3
SCK
SO
SI
TCL0
TCLO0
CLO
BUZ
Pin
Type
I/O
I
I
I/O
I/O
I/O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
3-bit I/O port. 1-bit or 3-bit read/write and test are
possible. Pull-up resistors are assignable to input pins by
software and are automatically disabled for output pins.
Pins are individually configurable as input or output.
2-bit input port. 1-bit or 2-bit read and test are possible.
Pull-up resistors are assignable by software.
4-bit input port. 1-bit or 4-bit read and test are possible.
Same as port 0
4-bit I/O ports. 1-, 4-, or 8-bit read/write and test are
possible. Pins are individually configurable as input or
output. 4-bit pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. The N-channel open-drain or push-pull output can
be selected by software (1-bit unit)
4-bit I/O port.
1-bit or 4-bit read/write and test are possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins. Pins are
individually configurable as input or output.
External interrupts with detection of rising and falling
edges
External interrupts with detection of rising or falling
edges
4-channel comparator input.
CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input
Serial interface clock signal
Serial data output
Serial data input
External clock input for timer/counter
Timer/counter clock output
CPU clock output
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19
MHz for buzzer sound
Number
8(9)
9(10)
10(11)
5(5)
6(6)
11-14
(12-15)
15(16)
16(17)
17(18)
18-21(20-23)
22-25(24-27)
26(28)
27(29)
28(30)
29(31)
5(5)
6(6)
11-14(12-15)
8(9)
9(10)
10(11)
15(16)
16(17)
17(18)
29(31)
Share Pin
SCK
SO
SI
INT0
INT1
CIN0–CIN3
TCL0
TCLO0
CLO
–
KS0
KS1
KS2
BUZ
P1.0
P1.1
P2.0–P2.3
P0.0
P0.1
P0.2
P3.0
P3.1
P3.2
P6.3
NOTE: Pn numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
1-10
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