MT8880CN Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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MT8880CN Datasheet PDF : 22 Pages
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MT8880C ISO2-CMOS
Steering Circuit
Guard Time Adjustment
Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred to
as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes vc (see Figure 5) to
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (tGTP), vc reaches the threshold
(VTSt) of the steering logic to register the tone pair,
latching its corresponding 4-bit code (see Figure 7)
into the Receive Data Register. At this point the GT
output is activated and drives vc to VDD. GT
continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.
The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:
tREC = tDP+tGTP
tID=tDA+tGTA
The value of tDP is a device parameter (see AC
Electrical Characteristics) and tREC is the minimum
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be
necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.
VDD
St/GT
R1
ESt
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
tGTA = (R1C1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
C1
R2
a) decreasing tGTP; (tGTP < tGTA)
VDD
VDD
St/GT
ESt
MT8880C
C1
Vc
R1
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
Figure 5 - Basic Steering Circuit
4
VDD
St/GT
tGTP = (R1C1) In [VDD / (VDD-VTSt)
tGTA = (RpC1) In (VDD/VTSt)
RP = (R1R2) / (R1 + R2)
C1
R1
R2
ESt
b) decreasing tGTA; (tGTP > tGTA)
Figure 6 - Guard Time Adjustment
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