DS1270AB Ver la hoja de datos (PDF) - Maxim Integrated

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componentes Descripción

Fabricante

DS1270AB

16M Nonvolatile SRAM

Maxim Integrated 

POWER-DOWN/POWER-UP CONDITION

DS1270Y/AB

SEE NOTE 11

POWER-DOWN/POWER-UP TIMING

PARAMETER

SYMBOL

VCC Fail Detect to CE and WE Inactive

tPD

VCC slew from VTP to 0V

tF

VCC slew from 0V to VTP

tR

VCC Valid to CE and WE Inactive

tPU

VCC Valid to End of Write Protection

tREC

MIN

150

150

TYP

(tA: See Note 10)

MAX UNITS NOTES

1.5

µs

11

µs

µs

2

ms

125

ms

PARAMETER

Expected Data Retention Time

SYMBOL MIN TYP

tDR

5

MAX

(tA=25°C)

UNITS NOTES

years

9

WARNING:

Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery

backup mode.

NOTES:

1. WE is high for a read cycle.

2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state.

3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE

going low to the earlier of CE or WE going high.

4. tDS is measured from the earlier of CE or WE going high.

5. These parameters are sampled with a 5 pF load and are not 100% tested.

6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output

buffers remain in a high-impedance state during this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in high-impedance state during this period.

6 of 8

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