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ATTINY28V Ver la hoja de datos (PDF) - Atmel Corporation

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ATTINY28V Datasheet PDF : 13 Pages
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Description
Block Diagram
The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-
tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves
throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize
power consumption versus processing speed. The AVR core combines a rich instruction
set with 32 general-purpose working registers. All the 32 registers are directly con-
nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architec-
ture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
Figure 1. The ATtiny28 Block Diagram
VCC
GND
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
XTAL1
XTAL2
8-BIT DATA BUS
INTERNAL
OSCILLATOR
OSCILLATOR
INTERNAL
CALIBRATED
OSCILLATOR
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
HARDWARE
STACK
GENERAL
PURPOSE
REGISTERS
Z
MCU CONTROL
REGISTER
TIMER/
COUNTER
INTERRUPT
UNIT
CONTROL
LINES
PROGRAMMING
LOGIC
ALU
STATUS
REGISTER
HARDWARE
MODULATOR
RESET
DATA REGISTER
PORTB
PORTB
DATA REGISTER
PORTD
DATA DIR
REG. PORTD
DATA REGISTER PORTA CONTROL
PORTA
REGISTER
PORTD
PORTA
The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O
lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an
8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with
internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops
the CPU while allowing the timer/counter and interrupt system to continue functioning.
The Power-down mode saves the register contents but freezes the oscillator, disabling
all other chip functions until the next interrupt or hardware reset. The wake-up or inter-
2 ATtiny28L/V
1062FS–AVR–07/06

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