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TDA1311AT

Stereo Continuous Calibration DAC (CC-DAC)

Philips Electronics 

Philips Semiconductors

Stereo Continuous Calibration DAC

(CC-DAC)

Preliminary specification

TDA1311A

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP.

Timing (see Fig.4)

tr

rise time

−

tf

fall time

−

tCY

bit clock cycle time

54

tBCKH

bit clock pulse width HIGH

15

tBCKL

bit clock pulse width LOW

15

tSU;DAT

data set-up time

12

tHD:DAT

data hold time to bit clock

2

tHD:WS

word select hold time

2

tSU;WS

word select set-up time

12

Analog outputs; pins VOL and VOR

VFS

full-scale voltage

1.8

TCFS

full-scale temperature

−

coefficient

Vos

offset voltage

(THD+N)/S total harmonic distortion plus

noise

VDD = VOL/ORmax

at 0 dB signal level; note 1

0.45

−

−

at −60 dB signal level; note 1 −

−

at −60 dB signal level;

−

A-weighted; note 1

−

at 0 dB signal level; f = 20 Hz −

to 20 kHz

−

tcs

current settling time to ±1 LSB

−

αcs

channel separation

75

|δIO|

unbalance between outputs note 1

−

|td|

time delay between outputs

−

S/N

signal-to-noise ratio at

A-weighted at code 0000H 86

bipolar zero

−

−

−

−

−

−

−

−

−

2.0

±400

0.50

−68

0.04

−30

3

−33

2

−65

0.05

0.2

80

0.2

±0.2

92

Note

1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz.

MAX.

12

12

−

−

−

−

−

−

−

2.2

−

0.55

−63

0.07

−24

6

−

−

−61

0.09

−

−

0.3

−

−

UNIT

ns

ns

ns

ns

ns

ns

ns

ns

ns

V

ppm

V

dB

%

dB

%

dB

%

dB

%

µs

dB

dB

µs

dB

1995 Dec 18

7

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