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ADRF6655

Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO

Analog Devices 

Broadband Up/Downconverting Mixer with

Integrated Fractional-N PLL and VCO

ADRF6655

FEATURES

Broadband active mixer with integrated fractional-N PLL

RF input frequency range: 100 MHz to 2500 MHz

Internal LO frequency range: 1050 MHz to 2300 MHz

Flexible IF output interface

Input P1dB: 12 dBm

Input IP3: 29 dBm

Noise figure (SSB): 12 dB

Voltage conversion gain: 6 dB

Matched 200 Ω output impedance

SPI serial interface for PLL programming

40-lead 6 mm × 6 mm LFCSP

GENERAL DESCRIPTION

The ADRF6655 is a high dynamic range active mixer with

integrated PLL and VCO. The synthesizer uses a programmable

integer-N/fractional-N PLL to generate a local oscillator input

to the mixer. The PLL reference input is nominally 20 MHz. The

reference input can be divided by or multiplied by and then

applied to the PLL phase detector. The PLL can support input

reference frequencies from 10 MHz to 160 MHz. The phase

detector output controls a charge pump whose output is integrated

in an off-chip loop filter. The loop filter output is then applied to an

integrated VCO. The VCO output at 2 × fLO is then applied to a local

oscillator (LO) divider as well as to a programmable PLL divider.

The programmable divider is controlled by an Σ-Δ modulator

(SDM). The modulus of the SDM can be programmed between

1 and 2047.

The broadband, active mixer employs a bias adjustment to allow

for enhanced IP3 performance at the expense of increased supply

current. The mixer provides an input IP3 exceeding 25 dBm

with 12 dB single sideband NF under typical conditions. The IIP3

can be boosted to ~29 dBm with roughly 20 mA of additional

supplied current. The mixer provides a typical voltage conversion

gain of 6 dB with a 200 Ω differential IF output impedance. The

IF output can be externally matched to support upconversion over

a limited frequency range.

The ADRF6655 is fabricated using an advanced silicon-germanium

BiCMOS process. It is packaged in a 40-lead, exposed-paddle,

Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a

−40°C to +85°C temperature range.

LON 37

LOP 38

GND 11

DATA 12

CLK 13

LE 14

GND 15

REFIN 6

GND 7

MUXOUT 8

GND GND VCCLO

36

35

34

FUNCTIONAL BLOCK DIAGRAM

LOSEL

BUFFER

NC NC GND

33

32

31

ADRF6655

30 GND

29 IP3SET

28 GND

27 VCCMIX

SPI

INTERFACE

×2

MUX

÷2

÷4

FRACTION

REG

MODULUS

INTEGER

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

N COUNTER

21 TO 123

BUFFER

LOSEL

PRESCALER

MUX

DIVIDER

÷2 OR ÷3

VCO

CORE

TEMP

SENSOR

–

+

PHASE

FREQUENCY

DETECTOR

3.3V LDO

CHARGE PUMP

250µA,

500µA (DEFAULT),

750µA,

1000µA

2.5V LDO

VCO LDO

26 INP

25 INN

24 GND

23 GND

22 VCCV2I

21 GND

1

VCC1

2

DECL1

3

4

5

9

10

39

40 16 17

18

19

20

CP GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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Fax: 781.461.3113

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