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C5002

Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG

Cypress Semiconductor 

C5002

Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG

Approved Product

Power Up Bi-Directional Pin Timing (all clock outputs)

Power Supply

CLK (0:9)

Hi-Z (tristate), inputs

Fig.1

Toggle, outputs

VDD

Note: a pull-up or logic high programming voltage will select a 66.6 MHz output clock frequency on that specific pin. A

logic low level will select a 33.3 MHz clock frequency in that specific pin.

Output Frequency Selections

The device contains 3 specific output mode type pins. They are:

REF-CLK0/S0

This pin powers up as a 33.3 or 66.6 MHz PCI clock. Via SMBus command byte 1 bit 4 it may be changed to be a

14.318 MHz clock. When it is acting as a PCI clock its frequency may be changed between 33 and 66 Mhz using SMBus

command byte 1 bit 3. The PCI clock may also be initially set at device power up using the bi-directional programming

capability of the pin (device pin number 27)

CLK (1:8)

These are dual frequency PCI clock pins that may be stopped enabled and have their frequency changed at power up

and then on the fly (at any time) via their respective SMBus register control bits.

CLK9/S9

This bit acts in the same manner as the CLK (1:8) bits. Additionally by selection in SMBus byte 3 Bits 5 and 6 it can

output both 16.5 Mhz or 8.25 Mhz on its pin. Like the other clock pins SMBus byte 3 Bit 6 is initially set (via the clocks bi-

directional; pin function) at power up depending on the level of the clocks pin.

NOTE: Clocks REF-CLK0/S0 (pin 27) and CLK1/S1 (pin 26) are powered from VDD1 (pin 28). This data sheet

characterizes the guaranteed performance of these 2 clocks with respect to jitter and skew. Designers that use this

device need to understand that if these 2 clocks are operated at different frequencies (e.g., pin 27 is set to the REF

output mode while pin 26 is enabled at either 33 pr 66 Mhz frequency mode) that the data sheet values of these clocks

will not be guaranteed. It is therefor prudent to disable the CLK1 output when the REF-CLK0/S0 output has been

programmed to output a 14.31818 Mhz clock to realize the devices best performance.

Cypress Semiconductor Corporation

525 Los Coches St.

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

Document#: 38-07014 Rev. **

5/4/2001

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