AK4101 Ver la hoja de datos (PDF) - Asahi Kasei Microdevices
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AK4101 Datasheet PDF : 28 Pages
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ASAHI KASEI
[AK4101]
OPERATION OVERVIEW
General Description
The AK4101 is a monolithic CMOS circuit that encodes and transmits audio and digital data according to the AES3,
IEC60958, S/PDIF and EIAJ CP1201 interface standards. There are four sets of stereo channels that can be transmitted
simultaneously. The chip accepts audio data and control data separately, multiplexes and biphase-mark encodes the data
internally, and drives it directly or through a transformer to a transmission line. There are two modes of operation:
asynchronous and synchronous. The asynchronous mode is fully software programmable through a serial control
interface and contains buffer memory for control data. The synchronous mode has dedicated pins for the important
control bits and a serial input port for the C, U and V bits.
Initialization
The AK4101 takes 8 bit clock cycles to initialize after PDN goes inactive. Also, for correct synchronization, MCLK
should be synchronized with LRCK but the phase is not critical. An internal reset will occur if the relationship between
MCLK and LRCK shifts by 3 MCLK cycles from their initial conditions.
MCLK and LRCK Relationship
For correct synchronization, MCLK and LRCK should be derived from the same clock signal either directly (as through
a frequency divider) or indirectly (for example, as through a DSP). The relationship of BICK to LRCK is fixed and
should not change. If MCLK or LRCK move such that they are shifted 3 or more MCLK cycles from their initial
conditions, the chip will generate an internal reset. After this reset, the TX outputs will transmit default values.
The following frequencies are supported for MCLK: 128fs/256fs/384fs/512fs.
CKS1
0
0
1
1
CKS0
0
1
0
1
MCLK
128fs
256fs
384fs
512fs
fs
28k-192kHz
28k-108kHz
28k-54kHz
28k-54kHz
Table 1. MCLK Frequency
Asynchronous Mode/ Synchronous Mode
1. Asynchronous Mode (software controlled)
The AK4101 can be configured in the asynchronous mode by connecting the ANS pin to logic “L”. In this mode the 16
to 24-bit audio samples are accepted through a configured audio serial port, and the channel status and user data through
a serial control host interface (SCI). The SCI allows access to internal buffer memory and control registers which are
used to store the channel status and user data. 4bytes per channel of user and channel status is stored. This data is
multiplexed with the audio data from the audio serial port, the parity bit is generated, and the bit stream is biphase-mark
encoded and driven through the RS422 line drivers. The CRCC code for the channel status is also generated according
to the professional mode definition in the AES3 standards. This mode also allows for software control for mute, reset,
audio format selection, clock frequency settings and output enables, via the serial host interface.
MS0076-E-01
- 11 -
2001/12
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