BD6369GUL Ver la hoja de datos (PDF) - ROHM Semiconductor
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BD6369GUL Datasheet PDF : 17 Pages
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BD6883GUL,BH6453GUL,BD6886GUL,BD6369GUL
Technical Note
10)
Testing an application board
When testing the IC on an application board, connecting a Capacitor to a pin with low impedance subjects the IC to
stress. Always discharge Capacitors after each process or step. Always turn the IC's power supply off before
connecting it to, or removing it from a jig or fixture, during the inspection process. Ground the IC during assembly
steps as an antistatic measure. Use similar precaution when transporting and storing the IC.
11)
Regarding the input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. P-N
junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic
diode or transistor. For example, the relation between each potential is as follows:
When GND > Pin A, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic diode and transistor.
Parasitic elements can occur inevitably in the structure of the IC. The operation of parasitic elements can result in
mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic
elements operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should
not be used.
Resistor
Transistor (NPN)
Pin A
Pin B C B
Pin B
Pin A
E
N
N P+
Parasitic element
P
P+ N
P substrate
GND
Parasitic
element
N P+
N
P
P+ N
P substrate
Parasitic elements
GND
GND
B
C
E
Parasitic
GND elements
Other adjacent elements
Fig.29 Example of Simple IC Architecture
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2012.03 - Rev.A
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