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LTC4441

N-Channel MOSFET Gate Driver

Linear Technology 

LTC4441/LTC4441-1

Applications Information

Driver Output Stage

A simplified version of the LTC4441/LTC4441-1’s driver-

output stage is shown in Figure 2.

VIN

Q1

DRVCC

LTC4441

P1

OUT

N1 RO

DRVCC

N3

N2

PGND

LOAD

INDUCTOR

CGD

POWER

MOSFET

CGS

4441 F02

Figure 2. Driver Output Stage

The pull-up device is the combination of an NPN transis-

tor, Q1, and a P-channel MOSFET, P1. This provides both

the ability to swing to rail (DRVCC) and deliver large peak

charging currents.

The pull-down device is an N-channel MOSFET, N1, with

a typical on resistance of 0.35Ω. The low impedance of

N1 provides fast turn-off of the external power MOSFET

and holds the power MOSFET’s gate low when its drain

voltage switches. When the power MOSFET’s gate is pulled

low (gate shorted to source through N1) by the LTC4441/

LTC4441-1, its drain voltage is pulled high by its load (e.g.,

inductor or resistor). The slew rate of the drain voltage

causes current to flow to the MOSFET’s gate through its

gate-to-drain capacitance. If the MOSFET driver does not

have sufficient sink current capability (low output imped-

ance), the current through the power MOSFET’s CGD can

momentarily pull the gate high and turn the MOSFET

back on.

A similar situation occurs during power-up when VIN is-

ramping up with the DRVCC regulator output still low. N1 is

off and the driver output, OUT, may momentarily pull high

through the power MOSFET’s CGD, turning on the power

MOSFET. The N-channel MOSFETs N2 and N3,shown in

Figure 2, prevent the driver output from going high in this

situation. If DRVCC is low, N3 is off. If OUT is pulled high

through the power MOSFET’s CGD, the gate of N2 gets

pulled high through RO. This turns N2 on, which then

pulls OUT low. Once DRVCC is >1V, N3 turns on to hold

the N2 gate low, thus disabling N2.

10

The pre-driver that drives Q1, P1 and N1 uses an adap-

tive method to minimize cross-conduction currents. This

is done with a 5ns nonoverlapping transition time. N1 is

fully turned off before Q1 is turned on and vice-versa using

this 5ns buffer time. This minimizes any cross-conduction

currents while Q1 and N1 are switching on and off without

affecting their rise and fall times.

Thermal Shutdown

The LTC4441/LTC4441-1 has a thermal detector that dis-

ables the DRVCC regulator and pulls the driver output low

when activated. If the junction temperature exceeds150°C,

the driver pull-up devices, Q1 and P1, turn off while the

pull-down device, N1, turns on briskly for 200ns to quickly

pull the output low. The thermal shutdown circuit has 20°C

of hysteresis.

Enable/Shutdown Input

The EN/SHDN pin serves two functions. Pulling this pin

below 0.45V forces the LTC4441/LTC4441-1 into shutdown

mode. In shutdown mode, the internal circuitry and the

DRVCC regulator are off and the supply current drops to

<12µA. If the input voltage is between 0.45V and 1.21V,

the DRVCC regulator and internal circuit power up but the

driver output stays low. If the input goes above 1.21V, the

driver starts switching according to the input logic signal.

The driver enable comparator has a small hysteresis of

120mV.

Blanking

In some switcher applications, a current sense resistor

is placed between the low side power MOSFET’s source

terminal and ground to sense the current in the MOSFET.

With this configuration, the switching controller must

incorporate some timing interval to blank the ringing

onthe current sense signal immediately after the MOSFET

is turned on. This ringing is caused by the parasitic induc-

tance and capacitance of the PCB trace and the MOSFET.

The duration of the ringing is thus dependent on the PCB

layout and the components used and can be longer than

the blanking interval provided by the controller.

44411fa

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